fpga相关问题列表-fpga - 码农岛

该标签暂无描述

Signal current cannot be synthesized, bad synchron

放荡不羁爱自由·2019-09-17 08:55·1 回答·问答

How to develop this algorithm?

叛逆·2019-09-16 18:49·1 回答·问答

pwm generation using fpga

Anthone·2019-09-13 10:11·1 回答·问答

Bad s_axi_bvalid, s_axi_wready, and s_axi_awready

Summer. ? 凉城·2019-09-12 16:45·1 回答·问答

Use of For loop in always block

爷的心禁止访问·2019-09-11 09:51·1 回答·问答

Please Explain these verilog code?

男人必须洒脱·2019-09-09 01:17·1 回答·问答

How to debug after implementation? My code that wo

倾城　Initia·2019-09-07 05:41·3 回答·问答

Counter with push button switch design using VHDL

女痞·2019-09-06 17:02·2 回答·问答

Too many comps of type “BUFGMUX” found to fit this

放我归山·2019-09-06 01:59·3 回答·问答

What is the exact criteria for an inout port, when

唯我独甜·2019-09-05 14:01·3 回答·问答

Why is my serial communication not working?

Ridiculous、·2019-09-04 15:22·2 回答·问答

Vivado Including Black Box Module

仙女界的扛把子·2019-09-03 12:07· 回答·问答

Can Vivado handle user defined physical types?

Root（大扎）·2019-08-31 04:56·1 回答·问答

finding power of a number

▲ chillily·2019-08-31 01:15·1 回答·问答

Why are the outputs of this pseudo random number g

爱情/是我丢掉的垃圾·2019-08-30 11:45·2 回答·问答

VHDL: Type of “variable” is incompatible with type

太酷不给撩·2019-08-27 07:08·2 回答·问答

Error in testbench

看我几分像从前·2019-08-26 07:51· 回答·问答

Why dynamic power consumption is always zero?

我只想做你的唯一·2019-08-26 01:58·1 回答·问答

Verilog: creating many registers of varying length

Juvenile、少年°·2019-08-26 00:16· 回答·问答

Provide input data to FPGA using USB

ら.Afraid·2019-08-25 02:26·2 回答·问答

上一页 1 2 3 4 5 6 下一页