system-verilog - 码农岛

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Warning: (vsim-7) Failed to open readmem file “mem

甜甜的少女心·2021-02-16 13:42· 回答·问答

How to write a module with variable number of port

SAY GOODBYE·2021-02-15 04:40· 回答·问答

Get system time in VCS

戒情不戒烟·2021-02-12 09:19· 回答·问答

Difference between @(posedge Clk); a<= 1'b1

Anthone·2021-01-01 16:39· 回答·问答

forcing a bit in a wire system verilog

走好不送·2020-12-23 19:34· 回答·问答

How to create random dynamic 2D arrays in SystemVe

Melony?·2020-12-23 17:19· 回答·问答

What is need of Assign/Deassign in Verilog?

Lonely孤独者°·2020-11-26 05:56· 回答·问答

How to write a makefile where the compiled object

Emotional °昔·2020-11-13 07:48· 回答·问答

Is a bad practice to use long nested if-else in as

The star\"·2020-10-20 09:01· 回答·问答

How to parameterize a case statement with don'

【Aperson】·2020-10-10 05:29· 回答·问答

System Verilog fork join - Not actually parallel?

▲ chillily·2020-10-04 08:11· 回答·问答

Automatic SystemVerilog variable size using interf

Summer. ? 凉城·2020-06-22 23:58·1 回答·问答

Automatic SystemVerilog variable size using interf

祖国的老花朵·2020-06-22 23:36· 评论·文章

Best way to access the uvm_config_db from the test

Juvenile、少年°·2020-05-23 15:40·2 回答·问答

Best way to access the uvm_config_db from the test

疯言疯语·2020-05-23 15:40· 评论·文章

Regex in SV or UVM

Lonely孤独者°·2020-03-06 05:08·1 回答·问答

Regex in SV or UVM

贼婆χ·2020-03-06 05:41· 评论·文章

How to define a parameterized multiplexer using Sy

祖国的老花朵·2020-02-14 05:26·3 回答·问答

How to define a parameterized multiplexer using Sy

我欲成王，谁敢阻挡·2020-02-14 06:16· 评论·文章

What is the difference between single (&) and doub

爷的心禁止访问·2020-02-10 09:54· 评论·文章

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