quartus - 码农岛

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Shift Right (srl) going wrong on VHDL Quartus II

祖国的老花朵·2019-09-06 14:51· 评论·文章

Shift Right (srl) going wrong on VHDL Quartus II

Evening l夕情丶·2019-09-06 14:32·1 回答·问答

What happens when there are multiple architectures

三岁会撩人·2019-08-13 04:17· 评论·文章

What happens when there are multiple architectures

▲ chillily·2019-08-13 04:09·1 回答·问答

Prevent compiler from optimizing logic away

forever°为你锁心·2019-08-12 04:55·2 回答·问答

Prevent compiler from optimizing logic away

祖国的老花朵·2019-08-12 04:47· 评论·文章

4bit transfer using synchronous d flip-flop( trans

戒情不戒烟·2019-08-11 17:05· 评论·文章

4bit transfer using synchronous d flip-flop( trans

迷人小祖宗·2019-08-11 16:11·1 回答·问答

QuartusII Synthesis: Enumerated type to State sign

啃猪蹄的小仙女·2019-08-06 12:37· 评论·文章

QuartusII Synthesis: Enumerated type to State sign

劳资没心，怎么记你·2019-08-06 12:40·1 回答·问答

Verilog: on left-hand side of assignment must have

走好不送·2019-07-24 08:05· 评论·文章

Verilog: on left-hand side of assignment must have

我欲成王，谁敢阻挡·2019-07-24 07:33·1 回答·问答

Issue with parameters in Modelsim

做个烂人·2019-07-12 03:42· 评论·文章

Issue with parameters in Modelsim

淡お忘·2019-07-12 03:31·1 回答·问答

verilog $readmemh takes too much time for 50x50 pi

迷人小祖宗·2019-05-06 20:23· 评论·文章

verilog $readmemh takes too much time for 50x50 pi

狗以群分·2019-05-06 20:33·1 回答·问答

ModelSim-Altera error

时光不老，我们不散·2019-02-13 12:34·1 回答·问答

ModelSim-Altera error

聊天终结者·2019-02-13 13:01· 评论·文章

Compiling *.vhdl into a library, using Altera Quar

戒情不戒烟·2019-01-28 08:44· 评论·文章

Compiling *.vhdl into a library, using Altera Quar

劳资没心，怎么记你·2019-01-28 08:23·2 回答·问答