Synthesis of wand as and gate

Question

Here I have multiple drivers for 1-bit port x. I want to resolve it by using wand net type. When I check out the schematics, only the least significant bit of input port is connected to port x, while remaining bits as unread. I want all bits of a to be used and assign to x port using AND gate to resolve multiple drivers.

module test(input [3:0]a, output [1:0]b);
  wire [3:0] d [1:0];

  wand temp;
  assign temp=a;

  inst inst_name (.x(temp),.y(d[1][3]),.z(b[1:0]));

  assign d[1] = {4'd15};
  assign d[0] = {4'd0};
endmodule

module inst (input wand x,y, output [1:0]z);
  assign z={x,y};
endmodule  

Answer 1

You can use for generate loop to achieve what you want:

generate
  for(i = 0; i < 4; i = i + 1) begin: wand_loop
    assign temp = a[i];
  end
endgenerate

This code will generate following structure:

Edit: as correctly pointed out by @mcleod_ideafix, if you define temp as a simple wire you can use following assignment: assign temp = &a; to achieve your goal.