Synthesis of `always` blocks

Question

The Verilog Golden Reference Guide on page 12 warns against unsynthesisable always blocks, and gives templates to be followed to reduce the chances of inadvertently creating unsynthesisable always blocks. However, the guide does not explain why, and in which situations, an always block is not synthesisable.

What are the most common reasons for an always block to not be synthesisable?

Answer 1

Basically every always block is describing a group of flip-flop, a group of latch, or a block of combinational circuit.

These three have different coding formats and should not be mixed, otherwise it may not be synthesizable. (sometime latch and combination circuit and be mixed but should be avoided)

Any always blocks that cannot be mapped to these three types of circuits are not synthesizable.

For example, mixed sensitive list of signals and edges is not synthesizable, because a flip-flop cannot be edge-tiggered and level-triggered at the same time.

More than two clocks are not synthesizable.

Embedded always blocks are not synthesizable.

Answer 2

Adding timing delays would not be synthesisable, but often used in verification. Also some tools will complain if you try to synthesise display statements.

always @* begin
 $display("%t", $realtime);
 #1 x = y;                  //Delayed by 1 time unit
 $display("%t", $realtime);
end