task in verilog

Question

I am trying to write a task that gives a variable paddr diffrent values:

module paddr1 ;
task paddr1;
input [10:0]paddr;
input clock;

 @(posedge clock)
begin
paddr=10
#100; 
paddr=20; 
#100; 
paddr=30; 
#100;  
paddr=40;
#100;   
paddr=50;
#100;   
paddr=60;
#100;  
paddr=70;
#100; 
paddr=80;
#100;

end
endtask
endmodule

I tried to call this task from test bench and wrote: paddr1 (paddr,clock);

It passes compilation But when I'm trying to run simulation I get an eror massage: Unresolved reference to 'paddr1'. Thank you for your answer the task is in a diffrent file then the test bench

Thank you Yaniv

Answer 1

You've a task inside a module. So, did you instantiate the module in the testbench? If you did, then you'll need to peek inside the module to call the task:

module tb();

  paddr1 U0; // instantiate module with the task in it...

  initial begin
     U0.paddr1(paddr,clock);
  end

endmodule

You've far more serious problems though. In verilog, arguments are passed to tasks by value. This means that the value of 'clock' will be fixed for the lifetime of the call to the task. Your task will never find a posedge of clock, and will wait forever. Also, you're assigning to a task input, which is not useful.

Answer 2

I'm guessing you want an initial block instead of a task. Wire up paddr and clock as ports to the module, then inside an initial begin block you modify paddr.

Of course you will still need to instantiate paddr1 somewhere to be useful.