I'm trying to implement a simple verilog code as below:
module test1(
input ACLK,
input RST,
output test_output1,
output test_output2
);
//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;
assign test_output1 = ACLK;
always @(posedge ACLK or negedge RST)
begin
if(!RST)
begin
//test_output1 <=0;
test_output2 <=0;
end
else
begin
//test_output1 <=0;
test_output2 <=1;
end
end
endmodule
I get the following error message when I try to synthesize it in Xilinx ISE:
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`
I am unable to resolve this error. Any help would be highly appreciated.
Add following modification:
You used
test_output1
in assign statement so it should be of type wire.You have already declared
test_output1
andtest_outpu2
as output and it is by default of type wire, so you just have to implicitly specify wire or reg according to usage,If you declare the directional of the port in the portlist, you must also declare the type. This is referred to as an ANSI style header.
There is also a non-ANSI style header that separates the portlist, directional, and type. If you are fallowing IEEE1364-1995 convention then you must use non-ANSI style and you cannot declare the type (e.g.
output reg test_output2;
is illegal, whileoutput test_output2; reg test_output2;
is legal). Since IEEE1364-2001 ANSI and non-ANSI style is supported (and the non-ANSI allowsoutput reg test_output2;
). All modern Verilog simulators are SystemVerilog (IEEE1800) simulators, therefore it is the designers choice. (ANSI style is more popular as it is less typing).ANSI style header:
Non-ANSI style header:
Note: With IEEE1364, you can not drive a
reg
with anassign
statement, it must be a net type. IEEE1800 has softened the rule the it is recommencedlogic
in stead ofreg
, but generally if you are going to useassign
then you should be assigning a net (e.g.wire
).