Force order of dependencies in a Makefile

Question

I have a Makefile that i want to use in parallel to compile a set of separate programs. It looks something like this:

compileall: program1 program2 program3
    @echo "Compilation completed"

program1 program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

I call it using gmake compileall -j3 and everything works fine. It runs daily as a part of our testing script.

Now, I've added a new target program1a that needs to be a part of this same make target and must not be performed at the same time as the program1 target. It is not important if it happens before or after, just not in parallel.

I know I could do something like:

compileall:
    +$(MAKE) program1 program2 program3
    +$(MAKE) program1a
    @echo "Compilation completed"

program1 program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

program1a:
    @echo "Compiling $@"
    $(MAKE) -C program1 A=true

Is there a better way to do this? I would like to not have to wait for the program2 and program3 to finish in order to start program1a compilation.

Answer 1

Not tested (tell me if this does not work), but you could do something like this :

compileall: program1 program2 program3
    @echo "Compilation completed"

program1: program1a
    @echo "Compiling $@"
    $(MAKE) -C $@

program1a program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

That way program1a should be built before program1 and make should be able to build program2 and program3 in parallel anyway.

---

EDIT: A little bit cleaner (thx @Beta):

compileall: program1 program2 program3
    @echo "Compilation completed"

program1: program1a

program1 program1a program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

---

EDIT 2: The only solution that comes to my mind to avoid dependencies is as follow.

Create 2 separate makefiles like this :

# Makefile1.mk

.NOTPARALLEL: # Force disabling of -j flag

all: program1 program1a

program1 program1a:
    @echo "Compiling $@"
    $(MAKE) -C $@

# Makefile

all: program1 program1a program2 program3

program1 program1a:
    $(MAKE) -f Makefile1.mk

program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@