Cache misses in an infinite loop with no memory re

Question

I am just running a while 1 loop and measuring cache miss.

int main() {
   while(1);
}

This particular process is tied to one cpu(using taskset) and this cpu is isolated, meaning no other process can get scheduled on the same cpu. Now I start measuring cache performance using perf and to my surprise last level cache miss is 42%.

22,579      cache-references                                            (20.82%)
8,976      **cache-misses         #   39.754 %** of all cache refs      (20.83%)
4,414      **LLC-load-misses      #   42.74%** of all LL-cache hits

I am surprised and I expected zero cache miss as I am not doing any memory operation. Any help/thoughts on this. cpu: model name : Intel(R) Xeon(R) CPU E5-2670 v3 @ 2.30GHz

Another experiment I did with giving a nano sleep of .1 milli second and cache miss reduced to less than 1%. I have no clue on whats going on.

Answer 1

Probably the perf counters are counting some events from kernel code in interrupt handlers. perf counter events aren't precise, so you'll get counts attributed to nearby instructions, and I guess for ops still in the pipeline when the kernel code did an iret. Or this may just be fully counting events that happened in kernel context, since it would be expensive to mess with perf-counters on every interrupt.

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Note that the cache-miss ratio only looks bad if you don't take into account how few cache accesses there are, total:

$ perf stat -e cycles,instructions,L1-dcache-loads,LLC-load-misses,LLC-loads,cache-references,cache-misses  ./infloop

Performance counter stats for './infloop':

 6,177,174,823      cycles                                                        (28.79%)
 6,167,361,425      instructions              #    1.00  insns per cycle          (43.00%)
     1,884,882      L1-dcache-loads                                               (42.93%)
        13,133      LLC-load-misses           #   19.41% of all LL-cache hits     (42.75%)
        67,676      LLC-loads                                                     (28.74%)
       391,004      cache-references                                              (28.50%)
        18,025      cache-misses              #    4.610 % of all cache refs      (28.42%)

   2.604227273 seconds time elapsed

Timed on a Conroe Core2Duo E6600 (since I bricked my Intel SnB motherboard with Intel's broken BIOS updates).

cache-references and cache-misses are "Kernel PMU events", while LLC-* and L1-* are "Hardware cache events", according to perf list. I'm not sure what that means.