Generating multiple lines to be compiled in Verilo

2019-07-23 22:55发布

I'm working on a VGA school-project that I'll synthesize on a FPGA. I'm working with Xilinx and using Verilog as a HDL. The project says that I have to generate a fixed number of particles, display them on screen and, by using the keyboard, I'll have to control the environment for these particles (like the wind, gravity etc.).

I can generate one particle with a size of 1 pixel (size is not important) by using:

  wire p1 =(posx>=part1x[13:4] && posx<=(part1x[13:4]+1) && posy>=part1y[12:4] && posy<=(part1y[12:4]+1));

By using this:

wire p1 =(posx>=part1x[13:4] && posx<=(part1x[13:4]+1) && posy>=part1y[12:4] && posy<=(part1y[12:4]+1));
wire p2 =(posx>=part2x[13:4] && posx<=(part2x[13:4]+2) && posy>=part2y[12:4] && posy<=(part2y[12:4]+2));
wire p3 =(posx>=part3x[13:4] && posx<=(part3x[13:4]+3) && posy>=part3y[12:4] && posy<=(part3y[12:4]+3));

three particles will be created.

How can I, for instance, generate 100 (or more) particles without having to write 100 lines of code?

标签: verilog
1条回答
走好不送
2楼-- · 2019-07-23 23:26

You can use a "for" loop to generate this. Here is a very simple example:

wire input[100];
wire output[100];
// ...
genvar i; 
generate 
  for (i = 0; i < 100; i = i+1)  begin
    assign output[i] = ~input[i];
  end  
endgenerate  

In order to apply this to your case, you might need to switch from using part1x, part2x etc., to using one big "array" and calculate offsets to it based on i.

Hope it helps. Good Luck!

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