I am getting an error while trying to pass the dat

Question

I am new to UVM and I am trying to verify a memory design where I am trying to run a write sequence multiple times followed by read sequence same number of times so that I could read the same addresses I am writing to, and compare. For this I tried to create a new class extended from uvm_object with a queue to store the addresses I am writing to, so that I could use them in read seq and I am instantiating this class in the scoreboard and then sending the handle of class to the read sequence via uvm_config_db, now the issue is I am able to store addresses in queue but unable to get the class handle in read sequence ......Is this the right way of checking or is there some better way to check the write and read back from memory, please help me !

entire code link (yet to complete): https://www.edaplayground.com/x/3iTr Relevant code snippets: This is the class I created to store the addresses

        class address_list extends uvm_object;
        reg[7:0]addr_q[$];
        function new(string name);
        super.new(name);
        endfunction 
        endclass;

In my scoreboard, I am passing the handle of class with address queue to the read sequence, here is the snippet from scoreboard

       virtual function void write(mem_seq_item pkt);
       if(pkt.wr_en==1)
       begin
       pkt_qu_write.push_back(pkt);
       addr.addr_q.push_back(pkt.addr);
     uvm_config_db#(address_list)::set(uvm_root::get(),"*","address",addr); 
       end
       if(pkt.rd_en==1)
       pkt_qu_read.push_back(pkt);
        `uvm_info(get_type_name(),$sformatf("Adder list is 
 %p",addr.addr_q),UVM_LOW)
    endfunction : write

In my read sequence, I am trying to get the handle

     virtual task body();
     repeat(3)
    `uvm_do(wr_seq)
     if(!uvm_config_db#(address_list)::get(this, " ", "address", addr_))
    `uvm_fatal("NO_VIF",{"virtual interface must be set for:",get_full_name(),".addr_"}); 

    `uvm_info(get_type_name(),$sformatf("ADDR IS %p",addr_),UVM_LOW)

     repeat(3)
     `uvm_do(rd_seq)
     endtask

Error-[ICTTFC] Incompatible complex type usage
mem_sequence.sv, 137 {line where i try to get from uvm_config_db}
Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the 
function. The type of the actual is 'class $unit::wr_rd_sequence', while 
the
type of the formal is 'class uvm_pkg::uvm_component'. Expression: this
Source info: uvm_config_db# 
(_vcs_unit__3308544630::address_list)::get(this, 
 " ", "address", this.addr_)

Answer 1

uvm_config_db is basically for passing configuration between components.

For purpose of passing data from scoreboard to sequence, you can use uvm_event.

• Trigger event in scoreboard using event.trigger(address_list)
• sequence wait for event using event.wait_for_trigger_data(address_list)

Answer 2

There are two problems with this line:

if(!uvm_config_db#(address_list)::get(this, " ", "address", addr_))

One is causing your error. One might lead to you not being able to find what you're looking for in the database.

This (literally this) is causing your error. You are calling get from a class derived from uvm_sequence. The first argument to get is expecting a class derived from uvm_component. Your problem is that a sequence is not part of the testbench hierarchy, so you cannot use a sequence as the first argument to a call to get (or set) in a uvm_config_db. Instead the convention is to use the sequencer that the sequence is running on, which is returned by a call to the sequence's get_sequencer() method. This solves your problem:

if(!uvm_config_db#(address_list)::get(get_sequencer(), "", "address", addr_))

This works because you used a wildcard when you called set.

Notice that I also removed the space from between the quotes. That might not give you a problem, because you used the wildcard when you called set, but in general this string should either be empty or should be a real hierarchical path. (The hierarchy input to the set and get calls is split between the first argument - a SystemVerilog hierarchical path - and the second - a string representing a hierarchical path).