How to define a VHDL component and package?

Question

Below I do have following two VHDL files. The file x.vhd with a component x which needs to be referenced (included) in the file top.vhd as a package.

-- x.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

package x_pkg is
    component my_x
        port(clk_clk          : in  std_logic    := '0';
             reset_reset_n    : in  std_logic    := '0';
    end component my_x;
end package x_pkg;

-----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity x is
    port (
        clk_clk               : in  std_logic         := '0';             --                             clk.clk        
        reset_reset_n         : in  std_logic         := '0';             --                           reset.reset_n
    );
end entity x;

architecture rtl of x is

This package needs to be referenced in following top-file:

-- top.vhd

library ieee;
use ieee.std_logic_1164.all;

library altera;
use altera.altera_syn_attributes.all;
use work.x_pkg.all;

entity EyeTracker_Top is
    port
    (
        Nios_Clk : in std_logic;
        Nios_Reset_n : in std_logic;
    );

end EyeTracker_Top;

architecture struct of EyeTracker_Top is

begin
M1 : my_x port map(Nios_Clk, Nios_Reset_n);            -- Here I get the error message!

After compiling, it get following error message:

***Error (12006): Node instance "M1" instantiates undefined entity "my_x"

---

What is the problem here? I guess there is something wrong with the package reference...

Thanks!

Answer 1

You are instantiating a component my_x. A component is just a declaration, a kind of empty shell. Every component instantiation must at some point be bound to an actual entity/architecture pair. This binding must be done with an explicit configuration. There are several ways to do this. One is to add:

for all: my_x use work.x(rtl);

in the declaration area of your architecture (between architecture and begin). Of course, the entity x and its architecture rtl must be compiled in the library you use as work before you can elaborate your top level.

The error message you got is difficult to understand because your tool tries to apply a default configuration strategy based on names: for unbound instances of components it searches an entity with the same name as the component. Because it found none, it complains about a missing entity while it is a component binding problem, that is, a missing configuration. A better tool would tell you that the M1 instance of component my_x is not bound.

A last note: if all this component stuff is too complicated for your needs, just get rid of it and directly instantiate your entity:

M1: entity work.x(rtl) port map(Nios_Clk, Nios_Reset_n);

and you will need no component declaration and no configuration.

There are basically two approaches:

• top-down design with components instantiations and configurations,
• bottom-up design with entity instantiations, no components and no configurations.

Understanding the differences between the two, their pros and cons is not easy. And there, a good VHDL book is probably better than questions and answers on stackoverflow.