VHDL Can you declare a package and an entity in th

Question

I tried to place the package and the entity in the same file but it did not compile it gave me an error saying: unknown identifier std_logic,

is there something i should do to put them in the same file?

Answer 1

The library declarations that you provided at the top of the file apply to the next design unit (which is probably your package).

When you start your entity, it is a new design unit and starts with an empty library space, so you have to put the library declarations in again. The same will happen if you put more than one entity in a given file - you have to put the library clauses in for each entity.

The VHDL compiler does not care at all what file anything is in, it only operates on the units within them. So you could have an entity in one file with some library declarations, and the architecture in another. The libraries do not then need to be redone in the architecture file, and they come in with the entity. If there are libraries that you only need for the architecture, they can be included just before the architecture statement (whether you are doing it in one file or two):

library ieee; 
use ieee.std_logic_1164.all;
entity foo
port ( 
   bar: std_logic; 
   etc...);
end entity;

-- could start a new file here, or not.
use ieee.numeric_std.all; -- not needed for the entity as it doesn't use unsigned types
architecture a of foo is
    signal counter : unsigned (10 downto 0);
begin
...
end architecture;

Answer 2

Yes, you can, but you have to remember that any library using declarations only apply to the next entity or package, not the entire file!

Effectively you need to write two files that can be compiled independently, and then copy the entire contents of one to the end of the other.