Use of forever and always statements

Question

Both the following codes generate a clock. I need to know if there is any use of forever loop other than clock generation? I have only come across forever in clock generation. If it only serves this purpose, isn't it useless?

initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end

initial begin
clk = 0 ;
always begin 
# 5 clk = ~clk;
end
end

Answer 1

Yes, forever loops have widespread usage in testbenches for design verification, particulalry in the industry standard methodology, UVM, and its predecessors (such as VMM). They are used in verification components such as drivers and monitors which make extensive use of tasks in SystemVerilog classes.

Answer 2

Your second code snippet is actually a syntax error. The difference between forever and always is that always can exist as a "module item", which is the name that the Verilog spec gives to constructs that may be written directly within a module, not contained within some other construct. initial is also a module item. always blocks are repeated, whereas initial blocks are run once at the start of the simulation.

forever is a procedural statement that can only be used in a procedural context. So it is legal to write initial forever or always forever, but not just forever.

The situation where forever becomes quite important is within tasks, which are procedural contexts, so use of always is not allowed. (Functions are procedural contexts as well, but may not contain delays, which makes it unlikely that forever will come in useful.

Answer 3

//i will show the difference;;;;;;; //we cannot use the forever block inside the initial block,but we can use forever block inside the intial block //code with error :

module stimulus(output reg a,b); 

 initial
 begin
  a = 1'b1;
  b = 1'b0;

  always
  begin
   #5 a = ~a;           //error when compiling
    #6 b = ~a;
  end

end

 initial
    #25 $stop;

endmodule




  // code with no error
module stimulus(output reg a,b); 

 initial
 begin
  a = 1'b1;
  b = 1'b0;

  always
  begin
   #5 a = ~a;    //no error when compiling
    #6 b = ~a;
  end

end

 initial
    #25 $stop;

endmodule