Create a Verilog Parser with Ruby

Question

I would like to create a Verilog parser written in Ruby for a university project

I know there are parser generators like Bison and Yacc.

Could anyone give me some advice on how to get started?

Answer 1

There do exist parser generators for Ruby too, e.g. racc. Start installing the racc gem and read the included documentation and examples.

Answer 2

I already have a very basic verilog parser (gem) written in ruby called verilog, if you could consider contributing to that instead, or it might give an idea of how to start.

I also have a gem called rubyit, which is command line utility to parse files with erb and generate the standard version of the file. Which can be used for extendable verilog templates, similar to generate statements but gives a flexible port list and ability to check the generated code.