Relocate the ARM exception vectors?

Question

How would I relocate the ARM exception vectors?

Basically, I need to be able to remap them in a way, so when the ARM core tries to execute the vector, it should execute the custom exception vector that is stored in kernel's RAM bit and not in the ROM that is at 0x0. Is that possible? Or am I meant to route the interrupts to the kernel from the ROM?

So essentially, is there a way of telling the ARM core, "here is the new address for your vector table"? I know that you can start the CPU in the high vector mode, but that's not what I'm looking for. I need to be able to set the vector base to a custom address dynamically.

Answer 1

A system register VBAR specifies the base address of the vector table. VBAR can be changed from PL1 or higher. Like most system registers, VBAR is also banked when Security Extension (TrustZone) is implemented.

Answer 2

This is highly dependent on the core you're working with.

Cortex-M3 chips can change the base address using the Vector Table Offset Register (VTOR) in the System Control Block. Some implementations might restrict possible addresses.

Of the "traditional" chips (ARM7/9, Cortex-A/R), I think none allow you to specify an arbitrary base, although most of them can switch between 00000000 and FFFF0000, and a few allow to use the "start of RAM" address.

However, if the chip has MMU, you can usually map a RAM page at FFFF0000 and copy your handlers there. I believe that's what Linux does.

Answer 3

For a cortex-A9 processor this can be done by making use of the VBAR register in the Cp15 co-processor register. The purpose of the Vector Base Address Register is to hold the base address for the Monitor exception vector.

 MRC p15, 0, <Rd>, c12, c0, 0    ; Read Secure or Non-secure Vector Base Address Register
 MCR p15, 0, <Rd>, c12, c0, 0    ; Write Secure or Non-secure Vector Base Address Register

Answer 4

More over, if your processor have security extension, you can take use of VBAR(Vector Base Address Register)

MCR p15, 0, <Rt>, c12, c0, 0

See the B4.1.156 in ARM Architecture Reference Manual.