I need a flip flop that reacts on the edges of two different signals. Something like this:
if(rising_edge(sig1)) then
bit <= '0';
elsif(rising_edge(sig2)) then
bit <= '1';
end if;
Does such a flip flop exist or is there some other technique i could use? I need this to be synthesizable on a Xilinx Virtex-5 FPGA. Thanks
What I'd usually do in this case is to keep a delayed version of both the control signals and generate a pulse one clock wide at the rising edge of each signal. I'd then use these pulses to drive a tiny FSM to generate the 'bit' signal. Here's some VHDL below.
I'm a lot more comfortable in verilog, so double check this VHDL (any comments appreciated).
waveforms http://img33.imageshack.us/img33/893/stackoverflowvhdlq.png
This code assumes that the clock is fast enough to capture all the control signal pulses. If the control signals are not synchronous with the clock, I'd keep a further delayed version of the delayed control signal (eg
sig_d2
) then make the flags fromsig_d1
andsig_d2
.