VHDL - Why does using the length attribute directl

Question

I have a VHDL function that returns a std_logic_vector representation of a record and I want the length of that std_logic_vector. I am able to use the length attribute directly on the function. Why does this produce a warning in ModelSim? Am I inviting subtle problems? Googling the warning text did not turn up anything I understood to be helpful.

my_function_returns_slv(my_record)'length;

** Warning: ../src/my.vhd(line#): (vcom-1515) Prefix of predefined attribute "length" is function call "my_function_returns_slv"

I've written the function to assemble the output by concatenating std_logic_vector representations of the record elements. The length of the record is fixed at compile time, but I do not want to hard code the length. I need the length to create signals for using the function output. So I can't just call 'length on the output of the function (ex: call 'length on a signal holding the function output) because it is not possible to declare an unconstrained signal to hold the output. I could write a similar function to calculate the length of the std_logic_vector, but that would add some significant code, especially for the number of records I have. Should I accept the ModelSim warning and carry on? Should I deal with the extra code from writing functions to assemble the bit width of my records? Is there a better solution altogether?

Helpful record pack/unpack subprograms I am making use of:

http://www.eda-twiki.org/twiki/pub/P1076/RecordReflectionToSlv/standard_functions.vhd

Thanks!

Answer 1

Using the 'length attribute directly on a function can be seen as just taking another part of the function result than the primary output, thus from a conceptual point of view there should be nothing wrong with that.

So I would accept the ModelSim warning, but also take it as an indication that the tool is worried about the construction, so I would check that my other tools, e.g. synthesis tools and code checkers, accept this use of an attribute directly on a function call.

Appears that you can avoid the ModelSim warning by making a function like:

function len(slv : std_logic_vector) return natural is
begin
  return slv'length;
end function;

and then this won't result in a ModelSim warning:

signal MY_LEN : natural := len(slv_not(CONST));

So being able to avoid the warning using such encapsulation confirms that the warning is a little flaky in the first place.

Answer 2

"I need the length to create signals for using the function output. So I can't just call 'length on the output of the function (ex: call 'length on a signal holding the function output) because it is not possible to declare an unconstrained signal to hold the output."

A fun work around for sizing signals is:

constant MY_CONST : std_logic_vector := my_function_returns_slv(my_record) ;
signal MySig : std_logic_vector(MY_CONST'range) := MY_CONST ; 

We have an LCS for VHDL-2017 that allows signals to be unconstrained and get their constraints from the initialization.