One makefile for two compilers

Question

I have two makefiles, for native and cross compilation. The only difference between them is compiler name:

# makefile
CC = g++
...

# makefile-cc
CC = arm-linux-gnueabihf-g++
...

To make native compilation, I execute make, to make cross-compilation, I execute make -f makefile-cc. I want to have one makefile, which should be executed using make for native compilation, and make cross for cross-compilation. What is correct syntax to do this, something like:

# makefile (C-like pseudo-code)
if cross
    CC = arm-linux-gnueabihf-g++
else
    CC = g++

Answer 1

not exactly what you wanted but you can read CC as an environment variable. consider the following Makefile:

all:
        echo $(CC)

and you can call it with CC=g++ make which gives you:

echo g++
g++

or call it with CC=arm-linux-gnueabihf-g++ make which gives you:

echo arm-linux-gnueabihf-g++
arm-linux-gnueabihf-g++

and the best part is you can put these in your ~/.bashrc as export CC=g++ and export CC=arm-linux-gnueabihf-g++ respectively and do the calling with only make.

Answer 2

Another way to do it which is more portable than the gnu make ifeq way is this one:

CROSS contains either arm-linux-gnueabihf- or is empty.

CC=$(CROSS)g++

CC will contain the expansion result.

Answer 3

You can assign/append variables for specific targets by using the syntax target:assignment on a line. Here is an example:

native: CC=cc
native:
    echo $(CC)

cross: CC=arm-linux-gnueabihf-g++
cross:
    echo $(CC)

calling

make native

(or just make, here) prints

echo cc
cc

and calling

make cross

prints

echo arm-linux-gnueabihf-g++
arm-linux-gnueabihf-g++

So you can use your usual compilation line with $(CC)

Answer 4

You can pass parameters to make.
e.g. make TARGET=native and make TARGET=cross then use this

ifeq ($(TARGET),cross)
        CC = arm-linux-gnueabihf-g++
else
        CC = g++
endif