I want to create a macro with multiple parameters just like $display.
My code looks like this but it doesn't work.
`define format_macro(A) \
$write("%s", $sformatf(A)); \
This is how I called format_macro.
`format_macro("variable = %d", variable)
How can I do this?
SystemVerilog now supports optional macro parameters, which allows you to create a clever kludge like this: http://ionipti.blogspot.com/2012/08/systemverilog-variable-argument-display.html
This allows you to modify the message format in the macro (prepend "ERROR", or maybe file and line number, or whatever else you like), which you can't do with the above approach of wrapping all parameters into parenthesis.
You are passing 2 arguments to your macro,
"variable = %d"
andvariable
, the macro only has 1 input defined. Reading the question it might not be multiple arguments that you want but a variable number.For a static list either have macro setup to format the text:
Or create the string first and pass as a single argument.
You can't. Verilog and SystemVerilog do not support variadic macros.
Here is a workaround if your goal is to use this for formatting strings or output, and you want to avoid having to type
$sformat
all over the place. You can define the macro to have a single argument, and combine that argument with$sformat
. The caveat with doing this is that you must wrap the argument in parentheses when using the macro.Note the
()
's for$sformatf
are not part of the macro:Then you can do this:
BTW, there is an excellent screencast here which shows how to customize messaging in UVM. In it, the author shows this macro technique, along with some other nice tips if you're using UVM.