Simplest way to generate Verilog code from Chisel

Question

What is the simplest way to generate Verilog code from existing Chisel code?

Would i have to create my own build file?

For example from a standalone scala file (AND.scala) like the following one..

import Chisel._

class AND extends Module {
  val io = IO(new Bundle {
    val a = Bool(INPUT)
    val b = Bool(INPUT)
    val out = Bool(OUTPUT)
  })
  io.out := io.a & io.b
}

I have the complete Chisel3 Toolchain installed under ubuntu 16.4.

Answer 1

See answer here: Is there a simple example of how to generate verilog from Chisel3 module?

In short, create a build.sbt file at the root of your project with the following in it:

scalaVersion := "2.12.8"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.1.6"

Add this code to AND.scala

object ANDDriver extends App {
  chisel3.Driver.execute(args, () => new AND)
}

Type sbt run on the command line at the root of your project.