Shifting 2D array Verilog

Question

I dont know what doesnt work on the following code, but it wont synthesize:

reg [7:0] FIFO [0:8];

always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0:8] <= {data_in, FIFO[1:8]};
    end
end

I tried to index the FIFO other ways too, but nothing works. Found this topic on a Xilinx forum but I just cant figue out what he wanted to tell with that. Here is the link:

http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368

thanks

Answer 1

the following will also work. It works whether FIFO is an unpacked array of packed (reg [7:0] FIFO [0:8]) or an packed array of packed (reg [7:0] [0:8] FIFO ).

reg [7:0] FIFO [0:8];

always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0] <= data_in;
       FIFO[1:8] <= FIFO[0:7];
    end
end

Answer 2

You have a miss understanding of how packed and unpacked arrays work. I recommend you read the IEEE1800-2012 section 7.4.1, 7.4.2, 7.4.4, & 7.4.5. Technically IEEE1800 is for SystemVerilog which is a super set of Verilog. The two are the same for arrays with static sizes and I find IEEE1800 has a better explanation and examples then the IEEE1364.

If you don't already have a copy of the LRM, then you can download it for free at the ieee.org website: IEEE Std 1800-2012

For the provided code, you cannot assign every element in an unpacked array in that manner. You have two choices: Use a for-loop to assign the unpacked portion of the array, or make your array double packed.

/* Using for-loop */
reg [7:0] FIFO [0:8];
integer i;
always@(posedge clk) begin
    if(wr & !rd & !full) begin
       for(i = 8; i > 0; i=i-i) begin
          FIFO[i] <= FIFO[i-1];
       end
       FIFO[0] <= data_in;
    end
end

/* Using double packed array */
reg [0:8] [7:0] FIFO; // NOTE: format and usage explained in IEEE1800-2012 7.4.5
always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0:8] <= {data_in,FIFO[0:7]};
    end
end