What is always followed by #(…) pound mean in Veri

Question

I am trying to learn Verilog, and in a simple clock generator example, I see the following code:

always #(cycle/2) clk ~= clk

I've seen always @(*) before but not pound (#). I tried to find it in the documentation, but all I could find was some reference to "real-valued ports" with no further elaboration.

Thanks for all your help!

Answer 1

It's a delay operation. It essentially just reads

always begin
   #(cycle/2) //wait for cycle/2 time
   clk ~= clk;
end

You might sometimes see this used with raw values, like #5 or #10, which means to wait 5 or 10 units of your timescale.