I have a preprocessor macro that represents a hierarchical path into my design.
Example:
`define HPATH top.chip.block
I need to construct a string which holds the value of `HPATH
, so in my example the string should equal top.chip.block
.
Is there a way to construct such a string?
None of the following attempts worked:
string hpath;
hpath = "`HPATH"; // Results in hpath = "`HPATH"
hpath = \"``HPATH\"; // Doesn't compile
hpath = `HPATH; // Doesn't compile
I want hpath
to be equivalent to doing this assignment hpath = "top.chip.block"
, but by using `HPATH
instead of specifying the path again.
I cannot use %m
because I need the string within my top-level UVM environment, not within a module.
A little more background: the reason I want to do this is because I am using backdoor register access in the UVM class library. The backdoor API requires setting the hdl_path to the blocks within the design, as a string. I already have `defines for the hierarchical paths and am trying to reuse those when specifying the hdl_paths so I don't have the same path defined twice. My testbench will use both the hierarchical path and the string path.
It's not possible to use a `define macro within a string literal. According to the SystemVerilog LRM:
However a string literal can be constructed by using a macro that takes an argument and including the quotes in the macro by using ``"`.
Again, from the LRM:
So this works:
The example code can be run here: http://www.edaplayground.com/s/4/879
I know this is an old thread, but I thought I'd share our solution. The use of the $sformatf allows additional information to be added if needed.
I think this is what you're looking for.
As toolic pointed out, the escape sequence %m will give you the current hierarchy when used in a $display statement so that may be a better option.