When i'm developing a linux driver, i've read about how to write linux kbuild makefile through this document
I know kbuild system use makefile variables such as obj-y obj-m to determine what to build and how to build.
But what i'm confused about is where does kbuild system really execute build process.In a word, if i have obj-m = a.o
, then where does kbuild system parse obj-m
and execute gcc a.c
?
Kbuild's Makefiles aren't the easiest to read, but here's a high-level untangling (using the 4.0-rc3 kernel):
The top-level Makefile does
, where
$(srctree)
is the top-level kernel directory.Kbuild.include
defines various common stuff and helpers. Among these isbuild
:build
is used with a command like$(MAKE) $(build)=dir
to perform the build for the directorydir
. It makes use ofscripts/Makefile.build
.Returning to the top-level Makefile, there's the following:
vmlinux-dirs
contains a list of subdirectories to build (init, usr, kernel, etc.).$(Q)$(MAKE) $(build)=<subdirectory>
will be run for each subdirectory.The rule above compiles object files for both the kernel image and modules. Further down in the top-level Makefile, there's some additional module-specific stuff:
Looking into
scripts/Makefile.build
(the Makefile used by$(build)
) now, it begins by initializing theobj-*
lists and various other lists:A bit further down, it loads in the Kbuild file where
obj-y
,obj-m
, etc., are set:Further down is the default rule, which has the
$(obj-y)
and$(obj-m)
lists as prerequisites:The
$(obj-y)
prerequisites come from$(builtin-target)
, which is defined as follows:The actual building seems to be performed by the following rule:
if_changed_rule
is fromKbuild.include
. The rule ends up running the following commands inMakefile.build
:$(cmd_cc_o_c)
seems to be the actual compilation command. The usual definition (there are two possibilities inMakefile.build
, AFAICS) seems to be the following:Unless set explicitly using e.g.
make CC=clang
,CC
defaults togcc
, as can be seen here in the top-level Makefile:The way I untangled this was by doing a CTRL-C during a kernel build and seeing where
make
reported the error. Another handymake
debugging technique is to use$(warning $(variable))
to print the value ofvariable
.