Use NMAKE to make all source in a directory?

Question

Using nmake, is it possible to have the makefile build all the .cpp files in the current directory automatically, without having to specify them individually?

So, instead of something like:

O = $(OBJ_DIR)/main.obj
{$(SOURCE_DIR)}.cpp{$(OBJ_DIR)}.obj:
    ---COMPILE $< HERE---

I'd like to avoid having to specify each obj to make. Can this be done?

Answer 1

You can run a shell command during nmakefile preprocessing, and then !include the output. Naturally the output needs to be in nmake format. Something like:

!if [bash -c "echo O = *.cpp" >sources.mak]
!error Failed to generate source list
!endif
!include sources.mak

all: $(O:.cpp=.obj)

.cpp.obj:
    ---COMPILE $< HERE---

I suspect that most people would not use bash to create sources.mak, but you get the idea.

Answer 2

I think this can be done with wild cards in GNU make (and IIRC you can run it on windows). Aside from that, I'm sorry but I don't known nmake.

Answer 3

.cpp.obj:
    $(CC) $(CFLAGS) $*.cpp

is a default rule that will automatically resolve .obj dependencies from .cpp files...

Answer 4

You can use a rule like this:

{src\mystuff}.c{tmp\src\mystuff}.obj::
    $(CC) /nologo $(CFLAGS) /c /Fotmp\src\mystuff\ $<

which will find and compile all the .c files in src\mystuff and put the object files in tmp\src\mystuff. Substitute .cpp for .c in your case.

Note that the first character on the second line should be a tab, not spaces.

Also, $(CC) is predefined by nmake to be cl, and you can add any compiler flags you need to $(CFLAGS), hard-code them in the rule or add a different variable there, as you prefer.

Answer 5

One possibility is to wrap the make in a script.

Either use a for loop, calling make on each .cpp file or construct a list of cpp files and use it as a parameter to the makefile.