How is a physical address generated in 8086?

Question

In the 8086 architecture, the memory space is 1 Mbyte in size and divided into logical segments of up to 64 Kbytes each.

i.e. it has 20 address lines thus the following method is used:

That the data segment register is shifted left 4 bits then added to the offset register

My question is: How we do the shift operation although all the registers are only 16 bits

Answer 1

Address translation is done internally by a special unit without using the registers available to user code to store intermediate results - it just fetches 16-bit values and does the translation inside - it is not reflected anywhere where the user code could observe it.

Answer 2

In hardware, register is a combination of flips-flops to store bits of information.

A hardware chip may have millions of register like that inside to store current instruction, current states, values... Only a small number of them is exposed to programs to store values. That's the idea. The specific behind each architecture is the manufacturer's secret so you'll never see any public document about this.

This is a simple hardware address calculator in verilog. The real implementation maybe much more complicated

module calc_phys_address(
                            phys_addr,  // Output of the counter
                            clk,        // clock Input
                            segment,    // segment
                            offset      // offset
);
    output reg [20:0] phys_addr;
    input             clk;
    input      [15:0] segment;
    input      [15:0] offset;

    always @(posedge clk)
        phys_addr[20:0] <= {segment[15:0], 4'b0} + offset[15:0];
endmodule