How to read a text file line by line in verilog?

Question

I have a SREC file which is a simple text file and I want to read it line by line in verilog. How can I do that?

Answer 1

The following reads through a file, 1 line per clock cycle: expected data format is one decimal number per line.

integer               data_file    ; // file handler
integer               scan_file    ; // file handler
logic   signed [21:0] captured_data;
`define NULL 0    

initial begin
  data_file = $fopen("data_file.dat", "r");
  if (data_file == `NULL) begin
    $display("data_file handle was NULL");
    $finish;
  end
end

always @(posedge clk) begin
  scan_file = $fscanf(data_file, "%d\n", captured_data); 
  if (!$feof(data_file)) begin
    //use captured_data as you would any other wire or reg value;
  end
end

Answer 2

Thank you for the solution. I modified it just a little to use 2 .txt file containing 32 HEX numbers on each row and found some difficulties on the way since I didn't understand what each line of code did. My findings were the following.

Just vars and regs declaration

////////I'm using inputs.txt and outputs.txt to read both lines at the same time
module Decryption_Top_Testbench;
////////TEXT DOC variables

integer               file_outputs    ; // var to see if file exists 
integer               scan_outputs    ; // captured text handler
integer               file_inputs     ; // var to see if file exists
integer               scan_inputs     ; // captured text handler

//TXT
reg [127:0] captured_outputs; ///Actual text obtained from outputs.txt lines
reg [127:0] captured_inputs;  ///Actual text obtained from inputs.txt lines

Opening both files

initial 
begin

 // TEXT FILE outputs///////////////////////

  file_outputs = $fopen("C:/outputs.txt", "r"); //Opening text file

//you should use the full path if you don't want to get in the trouble 
//of using environment vars 

    if (file_outputs == 0) begin               // If outputs file is not found
      $display("data_file handle was NULL"); //simulation monitor command
      $finish;
    end
  // TEXT FILE inputs///////////////////////
    file_inputs = $fopen("C:/inputs.txt", "r"); //Opening text file (inputs)
      if (file_inputs == 0) begin               //If inputs file is not found
        $display("data_file handle was NULL");
        $finish;
      end
end

At this part, I will read line by line in HEX format and store it in "captured_outputs" register and "captured_inputs" register.

///Since I'm using it just to simulate I'm not interested on a clock pulse,
/// I want it to happen all at the same time with whatever comes first

always @(* )
begin

   if (!$feof(file_outputs)) 
   begin
   ///!$feof means if not reaching the end of file
   ///file_outputs is always returning a different number other than "0" if the doc 
   ///has not ended. When reaching "0" it means the doc is over.
   ///Since both of my docs are the same length I'm only validating one of them
   ///but if you have different lenghts you should verify each doc you're reading

   ///

   scan_inputs = $fscanf(file_inputs, "%h\n", captured_inputs);        //Inputs Line text
   scan_outputs = $fscanf(file_outputs, "%h\n", captured_outputs);     //Outputs line text

   $display ("Line :[inputs: %h _ outputs: %h ]" captured_inputs, captured_outputs);  
   // Displaying each line at the simulation monitor

   ///$fscanf means formatted text, $scanf would read text ignoring the format
   /// %h\n means it should expect HEX numbers and the end of line character, that means 
   /// the line is over, but if you want to use a diff criteria 
   /// you can replace \n to whatever you may need 



   end

   else
   begin

   $finish;
   $fclose(file_outputs); //Closing files just in case to prevent wasting memory
   $fclose(file_inputs);

   end

end

I just wanted to contribute with something anybody who's starting to code in Verilog could understand and attach this great feature to his/her project.

Enjoy!