makefile aliases

Question

Please explain $@ $^ $ in the makefile below

LIBS  = -lkernel32 -luser32 -lgdi32 -lopengl32
CFLAGS = -Wall

# (This should be the actual list of C files)
SRC=$(wildcard '*.c')

test: $(SRC)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

Answer 1

SRC=$(wildcard '*.c')  

This just all your source file name ending with .c ie file1.c, file2.c file3.c etc.

in

test: $(SRC)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

$ is a way to define variables in Makefile

$@ is your target, in your case it is "test".

$^ is the list of all the prerequisites of the rule, including the names of the directories in which they were found

$< is the list of all dependencies

ref: https://www.gnu.org/software/make/manual/make.html#Automatic-Variables

Answer 2

This is what these two symbols mean:

• $@ is the target i.e. test
• $^ is the list of pre-requisites for the rule (which in this case is the expanded wild card list as specified in SRC=$(wildcard '*.c'))

All such variables are explained in the Automatic variables page of the GNU make manual.