How to print out a variable in makefile

Question

In my makefile, I have a variable 'NDK_PROJECT_PATH', my question is how can I print it out when it compiles?

I read Make file echo displaying "$PATH" string and I tried:

@echo $(NDK_PROJECT_PATH)
@echo $(value NDK_PROJECT_PATH)

Both gives me

"build-local.mk:102: *** missing separator.  Stop."

Any one knows why it is not working for me?

Answer 1

If you don't want to modify the Makefile itself, you can use --eval to add a new target, and then execute the new target, e.g.

make --eval='print-tests: @echo TESTS $(TESTS) ' print-tests

You can insert the required TAB character in the command line using CTRL-V, TAB

example Makefile from above:

all: do-something

TESTS=
TESTS+='a'
TESTS+='b'
TESTS+='c'

do-something:
        @echo "doing something"
        @echo "running tests $(TESTS)"
        @exit 1

Answer 2

Run make -n; it shows you the value of the variable..

Makefile...

all:
        @echo $(NDK_PROJECT_PATH)

Command:

export NDK_PROJECT_PATH=/opt/ndk/project
make -n 

Output:

echo /opt/ndk/project

Answer 3

The problem is that echo works only under an execution block. i.e. anything after "xx:"

So anything above the first execution block is just initialization so no execution command can used.

So create a execution blocl

Answer 4

As 'bobbogo' in the above answer pointed and as per the GNU Make manual, you can use info / warning / error to display text.

$(error   text…)
$(warning text…)
$(info    text…)

To print variables,

$(error   VAR is $(VAR))
$(warning VAR is $(VAR))
$(info    VAR is $(VAR))

when you use 'error' the make execution will stop after showing the error string

Answer 5

if you use android make (mka) @echo $(NDK_PROJECT_PATH) will not work and gives you error *** missing separator. Stop." use this answer if you are trying to print variables in android make

NDK_PROJECT_PATH := some_value
$(warning $(NDK_PROJECT_PATH))

that worked for me

Answer 6

You can print out variables as the makefile is read (assuming GNU make as you have tagged this question appropriately) using this method (with a variable named "var"):

$(info $$var is [${var}])

You can add this construct to any recipe to see what make will pass to the shell:

.PHONY: all
all: ; $(info $$var is [${var}])echo Hello world

Now, what happens here is that make stores the entire recipe ($(info $$var is [${var}])echo Hello world) as a single recursively expanded variable. When make decides to run the recipe (for instance when you tell it to build all), it expands the variable, and then passes each resulting line separately to the shell.

So, in painful detail:

• It expands $(info $$var is [${var}])echo Hello world
• To do this it first expands $(info $$var is [${var}])
  • $$ becomes literal $
  • ${var} becomes :-) (say)
  • The side effect is that $var is [:-)] appears on standard out
  • The expansion of the $(info...) though is empty
• Make is left with echo Hello world
  • Make prints echo Hello world on stdout first to let you know what it's going to ask the shell to do
• The shell prints Hello world on stdout.