How to arrange a Makefile to compile a kernel module with multiple .c files?
Here is my current Makefile. It was auto generated by KDevelop
TARGET = nlb-driver
OBJS = nlb-driver.o
MDIR = drivers/misc
EXTRA_CFLAGS = -DEXPORT_SYMTAB
CURRENT = $(shell uname -r)
KDIR = /lib/modules/$(CURRENT)/build
PWD = $(shell pwd)
DEST = /lib/modules/$(CURRENT)/kernel/$(MDIR)
obj-m += $(TARGET).o
default:
make -C $(KDIR) M=$(PWD) modules
$(TARGET).o: $(OBJS)
$(LD) $(LD_RFLAG) -r -o $@ $(OBJS)
ifneq (,$(findstring 2.4.,$(CURRENT)))
install:
su -c "cp -v $(TARGET).o $(DEST) && /sbin/depmod -a"
else
install:
su -c "cp -v $(TARGET).ko $(DEST) && /sbin/depmod -a"
endif
clean:
-rm -f *.o *.ko .*.cmd .*.flags *.mod.c
make -C $(KDIR) M=$(PWD) clean
-include $(KDIR)/Rules.make
The dependencies for $(TARGET).o can be multiple object files, one for each source file in your driver. Many other drivers use the += operator after the initial declaration of OBJS. For example,
The target rule would then expand to be
This is nice if there are more source files than comfortably fit on a line. But if there are only a small number of files, you can also define all the objects on a single line
In my case the project consists of 6 files:
monter_main.c
,monter_main.h
monter_cdev.c
,monter_cdev.h
monter_pci.c
,monter_pci.h
monter_main.c
is the main file of my module.Remember that you shouldn't have a file with the same name as the module you're trying to build (e.g.
monter.c
andmonter.ko
) unless you've got all code in that one file.Here are my Makefiles:
Makefile
Kbuild
I would assume that just listing more object files in the second line would do the trick.