VHDL guarded block 使用时出现Guarded signal unsupported

Question

按照《VHDL 数字电路设计教程》这本书中写的卫士块实现D触发器的程序，但是出现了问题，程序如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Dflipflop2Source is
port(d,clk,rst:in std_logic;
q:out std_logic);
end Dflipflop2Source;

architecture Behavioral of Dflipflop2Source is

begin
b1:block(clk'event and clk='1')
begin
q<= guarded '0' when rst='1' else d;
end block b1;

end Behavioral;
出现的为题为：
ERROR:HDLParsers:1074 - "D:/desktop/ISEVHDL/add1/Dflipflop2Source.vhd" Line 31. Guarded signal unsupported in block statement.
ERROR:HDLParsers:1024 - "D:/desktop/ISEVHDL/add1/Dflipflop2Source.vhd" Line 33. Guarded unsupported in signal assignment.

Answer 1

不属于RTL的设计，不要使用。