Is there a way in VHDL to have generic types? So for example I want to call a procedure but I'm not sure what type the signal has I want to give as paarameter, is it possible to declare the parameter as generic? Like in C++ you would use a Template.
procedure eq_checker(name : string; sig : ANYTHING); should : ANYTHING; at : time) is
if (at = now) then
if sig = should then
report "has same value" severity note;
else
report "has not same value" severity note;
end if;
end if;
end checker;
At least it should be possible to use different signal types as "sig".
if you don't know the type in the very moment you write e.g. a procedure, you can use a subtype. you can always change the subtype before synthesis. ok, this is only "somewhat generic" but still... it could look like that:
The Peter Ashenden and Jim Lewis book "VHDL-2008 - Just the new stuff" opens with
So, if your tool supports VHDL-2008 properly, you can now declare generic types, and you can declare generics on subprograms (not just entities).
And if they have followed the Ada model, the generics will be checked when you first compile them, not when you instantiate them, so that any instantiation that compiles will work, unlike the situation with C++ templates where bugs can lie dormant for years until you instantiate them in a particular way (because C++ templates are closer to macros than true generic metaprogramming)
Example : untested, but written following examples on p.17 of aforementioned book...