{var%20f='http://v.t.sina.com.cn/share/share.php?appkey=1515056452',u=z||d.location,p=['&url=',e(u),'&title=',e(t||d.title),'&source=',e(r),'&sourceUrl=',e(l),'&content=',c||'gb2312','&pic=',e(p||'')].join('');function%20a(){if(!window.open([f,p].join(''),'mb',['toolbar=0,status=0,resizable=1,width=440,height=430,left=',(s.width-440)/2,',top=',(s.height-430)/2].join('')))u.href=[f,p].join('');};if(/Firefox/.test(navigator.userAgent))setTimeout(a,0);else%20a();})(screen,document,encodeURIComponent,'','','https://www.manongdao.com/data/attach/logo/logo.png', '推荐 虎瘦雄心在 的问题《Faster 16bit multiplication algorithm for 8-bit MC》','https://www.manongdao.com/q-1331867.html','页面编码gb2312|utf-8默认gb2312'));){kind=link}
I'm searching for an algorithm to multiply two integer numbers that is better than the one below. Do you have a good idea about that? (The MCU - AT Tiny 84/85 or similar - where this code runs has no mul/div operator)
uint16_t umul16_(uint16_t a, uint16_t b)
{
uint16_t res=0;
while (b) {
if ( (b & 1) )
res+=a;
b>>=1;
a+=a;
}
return res;
}
This algorithm, when compiled for AT Tiny 85/84 using the avr-gcc compiler, is almost identical to the algorithm __mulhi3 the avr-gcc generates.
avr-gcc algorithm:
00000106 <__mulhi3>:
106: 00 24 eor r0, r0
108: 55 27 eor r21, r21
10a: 04 c0 rjmp .+8 ; 0x114 <__mulhi3+0xe>
10c: 08 0e add r0, r24
10e: 59 1f adc r21, r25
110: 88 0f add r24, r24
112: 99 1f adc r25, r25
114: 00 97 sbiw r24, 0x00 ; 0
116: 29 f0 breq .+10 ; 0x122 <__mulhi3+0x1c>
118: 76 95 lsr r23
11a: 67 95 ror r22
11c: b8 f3 brcs .-18 ; 0x10c <__mulhi3+0x6>
11e: 71 05 cpc r23, r1
120: b9 f7 brne .-18 ; 0x110 <__mulhi3+0xa>
122: 80 2d mov r24, r0
124: 95 2f mov r25, r21
126: 08 95 ret
umul16_ algorithm:
00000044 <umul16_>:
44: 20 e0 ldi r18, 0x00 ; 0
46: 30 e0 ldi r19, 0x00 ; 0
48: 61 15 cp r22, r1
4a: 71 05 cpc r23, r1
4c: 49 f0 breq .+18 ; 0x60 <umul16_+0x1c>
4e: 60 ff sbrs r22, 0
50: 02 c0 rjmp .+4 ; 0x56 <umul16_+0x12>
52: 28 0f add r18, r24
54: 39 1f adc r19, r25
56: 76 95 lsr r23
58: 67 95 ror r22
5a: 88 0f add r24, r24
5c: 99 1f adc r25, r25
5e: f4 cf rjmp .-24 ; 0x48 <umul16_+0x4>
60: c9 01 movw r24, r18
62: 08 95 ret
Edit: The instruction set is available here.
Well, mix of LUT and shift usually works
Something along the line, multiplying 8 bit entities. Lets consider them made up of two quads
just fill lut[] with results of multiplication. In your case depending on memory you could go with quads (256 sized LUT) or with bytes (65536 size LUT) or anything in between
Summary
aandb(Original proposal)1. Consider swapping
aandbOne improvement would be to first compare a and b, and swap them if
a<b: you should use asbthe smaller of the two, so that you have the minimum number of cycles. Note that you can avoid swapping by duplicating the code (if (a<b)then jump to a mirrored code section), but I doubt it's worth.2. Trying to avoid conditional jumps (Not successful optimization)
Try:
From Sergio's feedback, this didn't bring improvements.
3. Reshaping of the input formula
Considering that the target architecture has basically only 8bit instructions, if you separate the upper and bottom 8 bit of the input variables, you can write:
Now, the cool thing is that we can throw away the term
a1 * b1 * 0xffff, because the0xffffsend it out of your register.Furthermore, the
a0*b1anda1*b0term can be treated as 8bit multiplications, because of the0xff: any part exceeding 256 will be sent out of the register.So far exciting! ... But, here comes reality striking:
a0 * b0has to be treated as a 16 bit multiplication, as you'll have to keep all resulting bits.a0will have to be kept on 16 bit to allow shift lefts. This multiplication has half of the iterations ofa * b, it is in part 8bit (because of b0) but you still have to take into account the 2 8bit multiplications mentioned before, and the final result composition. We need further reshaping!So now I collect
b0.But
So we get:
If N were the cycles of the original
a * b, now the first term is an 8bit multiplication with N/2 cycles, and the second a 16bit * 8bit multiplication with N/2 cycles. Considering M the number of instructions per iteration in the originala*b, the 8bit*8bit iteration has half of the instructions, and the 16bit*8bit about 80% of M (one shift instruction less for b0 compared to b). Putting together we haveN/2*M/2+N/2*M*0.8 = N*M*0.65complexity, so an expected saving of ~35% with respect to the originalN*M. Sounds promising.This is the code:
Also, the splitting in 2 cycles should double, in theory, the chance of skipping some cycles: N/2 might be a slight overestimate.
A tiny further improvement consist in avoiding the last, unnecessary shift for the
avariables. Small side note: if either b0 or b1 are zero it causes 2 extra instructions. But it also saves the first check of b0 and b1, which is the most expensive because it cannot check thezero flagstatus from the shift operation for the conditional jump of the for loop.4. Removing duplicated shift
Is there still space for improvement? Yes, as the bytes in
a0gets shifted two times. So there should be a benefit in combining the two loops. It might be a little bit tricky to convince the compiler to do exactly what we want, especially with the result register.So, we process in the same cycle
b0andb1. The first thing to handle is, which is the loop exit condition? So far usingb0/b1cleared status has been convenient because it avoids using a counter. Furthermore, after the shift right, a flag might be already set if the operation result is zero, and this flag might allow a conditional jump without further evaluations.Now the loop exit condition could be the failure of
(b0 || b1). However this could require expensive computation. One solution is to compare b0 and b1 and jump to 2 different code sections: ifb1 > b0I test the condition onb1, else I test the condition onb0. I prefer another solution, with 2 loops, the first exit whenb0is zero, the second whenb1is zero. There will be cases in which I will do zero iterations inb1. The point is that in the second loop I knowb0is zero, so I can reduce the number of operations performed.Now, let's forget about the exit condition and try to join the 2 loops of the previous section.
Thanks Sergio for providing the assembly generated (-Ofast). At first glance, considering the outrageous amount of
movin the code, it seems the compiler did not interpret as I wanted the hints I gave to him to interpret the registers.Inputs are: r22,r23 and r24,25.
AVR Instruction Set: Quick reference, Detailed documentation
5. Unrolling the loop: The "optimal" assembly
With all this information, let's try to understand what would be the "optimal" solution given the architecture constraints. "Optimal" is quoted because what is "optimal" depends a lot on the input data and what we want to optimize. Let's assume we want to optimize on number of cycles on the worst case. If we go for the worst case, loop unrolling is a reasonable choice: we know we have 8 cycles, and we remove all tests to understand if we finished (if b0 and b1 are zero). So far we used the trick "we shift, and we check the zero flag" to check if we had to exit a loop. Removed this requirement, we can use a different trick: we shift, and we check the carry bit (the bit we sent out of the register when shifting) to understand if I should update the result. Given the instruction set, in assembly "narrative" code the instructions become the following.
Branching takes 1 instruction if no jump is caused, 2 otherwise. All other instructions are 1 cycle. So b1 state has no influence on the number of cycles, while we have 9 cycles if b0 = 1, and 8 cycles if b0 = 0. Counting the initialization, 8 iterations and skipping the last update of a0 and a1, in the worse case (b0 = 11111111b), we have a total of
8 * 9 + 2 - 2 =72 cycles. I wouldn't know which C++ implementation would convince the compiler to generate it. Maybe:But, given the previous result, to really obtain the desired code one should really switch to assembly!
Finally one could also consider a more extreme interpretation of the loop unrolling: the sbrc/sbrs instructions allows to test on a specific bit of a register. We can therefore avoid shifting b0 and b1, and at each cycle check a different bit. The only problem is that those instructions only allow to skip the next instruction, and not for a custom jump. So, in "narrative code" it will look like this:
While the second substitution allows to save 1 cycle, there's no clear advantage in the second substitution. However, I believe the C++ code might be easier to interpret for the compiler. Considering 8 cycles, initialization and skipping last update of a0 and a1, we have now 64 cycles.
C++ code:
Note that in this implementation the 0x01, 0x02 are not a real value, but just a hint to the compiler to know which bit to test. Therefore, the mask cannot be obtained by shifting right: differently from all other functions seen so far, this has really no equivalent loop version.
One big problem is that
It should be just a sum of the upper register of
rwith the lower register ofa. Does not get interpreted as I would like. Other option:6. Convincing the compiler to give the optimal assembly
We can also keep
aconstant, and shift instead the resultr. In this case we processbstarting from the most significant bit. The complexity is equivalent, but it might be easier for the compiler to digest. Also, this time we have to be careful to write explicitly the last loop, which must not do a further shift right forr.A non-answer, tinyARM assembler (web doc) instead of C++ or C. I modified a pretty generic multiply-by-squares-lookup for speed (< 50 cycles excluding call&return overhead) at the cost of only fitting into AVRs with no less than 1KByte of RAM, using 512 aligned bytes for a table of the lower half of squares. At 20 MHz, that would nicely meet the
2 max 3 usectime limit still not showing up in the question proper - but Sergio Formiggini wanted 16 MHz. As of 2015/04, there is just one ATtiny from Atmel with that much RAM, and that is specified up to 8 MHz … (Rolling your "own" (e.g., from OpenCores) your FPGA probably has a bunch of fast multipliers (18×18 bits seems popular), if not processor cores.)For a stab at fast shift-and-add, have a look at shift and add, factor shifting left, unrolled 16×16→16 and/or improve on it (wiki post). (You might well create that community wiki answer begged for in the question.)
The compiler might be able to produce shorter code by using the ternary operator to choose whether to add 'a' to your accumulator, depends upon cost of test and branch, and how your compiler generates code.
Swap the arguments to reduce the loop count.
Many years ago, I wrote "forth", which promoted a compute rather than branch approach, and that suggests picking which value to use,
You can use an array to avoid the test completely, which your compiler can likely use to generate as a load from offset. Define an array containing two values, 0 and a, and update the value for a at the end of the loop,
Yeah, evil. But I don't normally write code like that.
Edit - revised to add swap to loop on smaller of op1 or op2 (fewer passes). That would eliminate the usefulness of testing for an argument =0.
One approach is to unroll the loop. I don't have a compiler for the platform you're using so I can't look at the generated code, but an approach like this could help.
The performance of this code is less data-dependent -- you go faster in the worst case by not checking to see if you're in the best case. Code size is a bit bigger but not the size of a lookup table.
(Note code untested, off the top of my head. I'm curious about what the generated code looks like!)
Update:
Depending on what your compiler does, the UMUL16_STEP macro can change. An alternative might be:
With this approach the compiler might be able to use the
sbrcinstruction to avoid branches.My guess for how the assembler should look per bit, r0:r1 is the result, r2:r3 is
aand r4:r5 isb:This should execute in constant time without a branch. Test the bits in
r4and then test the bits inr5for the higher eight bits. This should execute the multiplication in 96 cycles based on my reading of the instruction set manual.At long last, an answer, if a cheeky one: I couldn't (yet) get the AVR-C-compiler from the GCC fit it into 8K code. (For an assembler rendition, see AVR multiplication: No Holds Barred).
The approach is what everyone who used Duff's device tried for a second attempt:
use a switch. Using macros, the source code looks entirely harmless, if massaged: