What is meant by the FENCE instruction in the RISC

Question

While going through the RISC-V ISA, I have seen an instruction in the memory model section (FENCE instruction). What does it mean exactly?

Answer 1

I've found one case when using FENCE instruction is just necessary. Example:

1. Some module in a SoC generates interrupt by writting value into CSR 0x783 (MIPI) via HostIO bus.
2. Firmware jumps to the interrupt handler.
3. Handler tries to reset 'pending' bit in a user implemented device by writting 1 into register.
4. Such operation was compiled as a 'store' instruction with immediate value =1.
5. As result, if I don't implement FENCE at the beginning of the handler I have some garbage value instead of proper immediate argument of the instruction.

Answer 2

The RISC-V ISA uses a relaxed memory model where the order of loads and stores performed by one thread may be different when seen by another. This is done to enable techniques to increase memory system performance.

For example, Thread 1 may execute:

• Load A
• Store B
• Store C

But Thread 2 could see the loads and the stores out of order with regard to the first thread:

• Store C
• Load A
• Store B

The FENCE ensures that all operations before the fence are observed before any operation after the fence. So if the above changed to:

Thread 1:

• Load A
• Store B
• FENCE
• Store C

Then Thread 2 would be guaranteed to see the load to A and the store to B before the store to C, but still could see the store to B before the load of A.

Thread 2:

• Store B
• Load A
• Store C

Source: http://riscv.org/download.html (User-Level ISA Spec v2.0 page 19)