Why doesn't the Linux kernel see the cache siz

Question

I want to play around with cache sizes in my gem5 simulator to see how it affects performance of programs, and possibly tune programs at runtime.

As a sanity check, I tried to check that the command lines arguments I used were working , and so I tried the various methods proposed at: https://superuser.com/questions/55776/finding-l2-cache-size-in-linux/1298808#1298808

cat /sys/devices/system/cpu/cpu0/cache/index2/size
getconf LEVEL2_CACHE_SIZE

But I observed that:

• the file /sys/devices/system/cpu/cpu0/cache/index2/size does not exist
• getconf is empty

Why is that?

I am certain however that the caches are being, since I've benchmarked simple programs, and the cycle counts increase when I decrease the caches.

For example, my base command is:

M5_PATH='/data/git/linux-kernel-module-cheat/gem5/gem5-system'  '/data/git/linux-kernel-module-cheat/gem5/gem5/build/ARM/gem5.opt'  '/data/git/linux-kernel-module-cheat/gem5/gem5/configs/example/fs.py' --command-line='earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 rw loglevel=8 mem=512MB root=/dev/sda nokaslr norandmaps printk.devkmsg=on printk.time=y' --disk-image='/data/git/linux-kernel-module-cheat/buildroot/output.arm-gem5~/images/rootfs.ext2' --dtb-file='/data/git/linux-kernel-module-cheat/gem5/gem5/system/arm/dt/armv7_gem5_v1_1cpu.dtb' --kernel='/data/git/linux-kernel-module-cheat/buildroot/output.arm-gem5~/build/linux-custom/vmlinux' --machine-type=VExpress_GEM5_V1 --num-cpus=1  --caches --l1d_size=1024 --l1i_size=1024 --l2cache --l2_size=1024 --l3_size=1024 --cpu-type=HPI

With those tiny caches, running the following:

m5 resetstats && dhrystone 10000 && m5 dumpstats

takes 175M cycles, and only 16M cycles if I use the exact same command but with huge caches of size 1024MB.

I observe a similar behavior for x86.

I'm using this testing infrastructure: https://github.com/cirosantilli/linux-kernel-module-cheat/tree/05d8a324f74849f03404eb847f8da748e2e4502c#gem5-change-system-parameters which implies:

• gem5 commit: fbe63074e3a8128bdbe1a5e8f6509c565a3abbd4
• Linux kernel v4.15 with configuration: https://github.com/cirosantilli/linux-kernel-module-cheat/blob/05d8a324f74849f03404eb847f8da748e2e4502c/kernel_config_arm-gem5

Related thread on the mailing list: http://gem5-users.gem5.narkive.com/4xVBlf3c/verify-cache-configuration

For comparison, QEMU v2.11.0 x86 did show the cache sizes, but not the ARM one.

Maybe for ARM we would need to modify the bootloaders to tell that to kernel? But I don't know how those things work very well:

• https://github.com/gem5/gem5/blob/fbe63074e3a8128bdbe1a5e8f6509c565a3abbd4/system/arm/simple_bootloader/simple.S
• https://github.com/gem5/gem5/blob/fbe63074e3a8128bdbe1a5e8f6509c565a3abbd4/system/arm/aarch64_bootloader/boot.S

Answer 1

I have been told that:

gem5 doesn't implement the cache size discovery registers.

The problem is that it is really hard to configure them in the general case, and they might not even be able to represent the hierarchy in gem5.