When MCR or MRC instructions execute with different cRm or opt2, then what is the status of cRn register? For example if run:
asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r"(val))
or
asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r"(val))
then, which register's value will be changed c9 or c13? and what is the role of last option(0 or 2)?.here
The MCR and MRC instructions are generic coprocessor instructions. What these instructions do depends on the particular hardware you're using, what coprocessors it has, and the values of the opcode and coprocessor register operands (opcode1, opcode2, CRn and CRm). The coprocessor register operands don't necessarily refer to actual coprocessor registers, and so are effectively additional opcode operands.
To find out what an MCR/MRC nstructions does, you need to look up it up in the hardware specific documentation the particular CPU this code is meant to run under. So with your examples we need to look in the Cortex-A7's documentation for coprocessor 15, which is the System Control "coprocessor". This page lists the System Control registers that can be accessed using these instructions in CRn, opcode1, CRm, opcode2 order.
In both your examples CRn is c9, and looking that up in the documentation leads to us to a page describing mostly performance monitoring related registers. In your first example opcode1 is 0, CRm is 13, and opcode2 is 0, which this page tells us that the instruction writes to the PMCR or Performance Monitor Control Register. With the second example opcode1 is 0, CRm is 13, and opcode2 is 2, meaning it accesses the PMNCNTENCLR or Count Enable Clear Register.
You're better off thinking that op1, op2, crn and crm form a certain register address. The latter instruction sets the co-processor 15 register 0, c9, c13, 2 (PMXEVCNTR, Performance Monitors Event Count Register) to the value contained in the register the C compiler decides to use for variable 'val'.
For other than performance counter registers: B3.17.1 CP15 register summary by coprocessor register number Figure B3-26 summarizes the grouping of CP15 registers by primary coprocessor register number for a VMSAv7 implementation.
About debug registers, there is a description: C6.4.1 Using CP14 to access debug registers Accesses to registers that are visible in the CP14 interface generally use the following coprocessor instructions: • MRC for read accesses. • MCR for write accesses.