This instruction forces the core to
wait for all pending explicit data accesses to complete before any
additional instructions stages can be executed. There is no effect on
pre-fetching of instructions.
Data Memory Barrier (DMB)
This
instruction ensures that all memory accesses in program order before
the barrier are observed in the system before any explicit memory
accesses that appear in program order after the barrier. It does not
affect the ordering of any other instructions executing on the core,
or of instruction fetches.
DSB
is superset ofDMB
so it can be replaced by aDSB
if performance is not a concern.From Cortex-A Series Programmer's Guide: