$zero on MIPS really hardware zero?

Question

I'm kind of firm with x86-64 assembly (not an expert maybe), but many aspects are similar from one platform's assembler to the next, so I'm also trying to answer questions that are not actually in my range of knowledge, and I've stumbled upon several questions about MIPS assembly.

This wakened my interest in details, so I've checked several online ressources for detailed information. mips.com has a lot to read, but just for my quick information:

Is the $zero register just conventional zero or hardware zero?

Some sources say it is conventionally zero, others claim it is always zero. Or do the latter simply assume it is zero, because it conventionally is?

Thanks in advance for clarification (and/or pointers to a specific doc from MIPS' site, so I don't need to crawl information that I actually don't need).

Answer 1

The definitive answer to this can be found in MIPS32® Architecture for Programmers Volume I: Introduction to the MIPS32® Architecture (pdf), available at mips.com (registration required). According to Section 2.4.8.1 in that document:

Two of the CPU general-purpose registers have assigned functions:

• r0 is hard-wired to a value of zero, and can be used as the target register for any instruction whose result is to be discarded. r0 can also be used as a source when a zero value is needed.

• r31 is the destination register used by JAL, BLTZAL, BLTZALL, BGEZAL, and BGEZALL without being explicitly specified in the instruction word. Otherwise r31 is used as a normal register.

The remaining registers are available for general-purpose use.

Answer 2

The top 5 references say it's a hardw(are|ired) zero.

And, however surprising it may be, MIPS is not alone in having such an odd register.

For comparison, TI's MSP430 has two special registers: R2 (status register) and R3 (constant generator). When you read a memory operand through them (or read R3 directly), you fetch one of the following predefined constants: -1, 0, 1, 2, 4, 8. The constant depends on the register number and on the kind of access (direct, indexed, indirect, indirect+autoincrement). This reduces code size and (AFAIR) execution time because otherwise immediate constants occupy 16 bits and need to be fetched.