My SSE-FPU generates the following NaNs:
- When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD and one of both operands is a NaN, the result has the sign of the NaN-operand and the lower 51 bits of the mantissa of the result is loaded with the lower 51 bits of the mantissa of the NaN-operand.
- When both operations are NaN, the result is loaded with the sign of the destination-register and the lower 51 bits of the result-mantissa is loaded with the lower 51 bits of the destination-register before the operation. So the associative law doesn't count when doing multiplications on two NaN-operands!
- When I do a SQRTSD on a NaN-value, the result has the sign of the NaN-operand and the lower 51 bits of the result is loaded with the lower 51 bits of the operand.
- When I do a multiplication of infinity with zero or infinity, I always get -NaN as a result (binary representation 0xFFF8000000000000u).
- If any operand is a signalling NaN, the result becomes a quiet NaN if the exception isn't masked.
Is this behaviour determined anywhere in the IEEE-754-standard?
NaN have a sign and a payload, together are called the information contained in the NaN.
The whole point of NaNs is that they are "sticky" (maybe Monadic is a better term?), once we have a NaN in an expression the whole expression evaluate to NaN.
Also NaNs are treated specially when evaluating predicates (like binary relations), for example if
a
is NaN, then it is not equal to itself.Point 1
From the IEEE 754:
Point 2
From the IEEE 754:
No floating point operation has ever been associative.
I think you were looking for the term commutative though since associativity requires at least three operands involved.
Point 3
See point 4
Point 4
From IEEE 754:
Point 5
From IEEE 754:
Due to its relevance, the IEEE 754 standard can be found here.