Approximate cost to access various caches and main

Question

Can anyone give me the approximate time (in nanoseconds) to access L1, L2 and L3 caches, as well as main memory on Intel i7 processors?

While this isn't specifically a programming question, knowing these kinds of speed details is neccessary for some low-latency programming challenges.

Answer 1

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Answer 5

+ 10-11 [usec] XFER-LATENCY-down DeviceToHost |

Answer 6

| | PCIe-2.0 ( 4x) | ~ 4 GB/s over 4-Lanes ( PORT #2 ) | | PCIe-2.0 ( 8x) | ~16 GB/s over 8-Lanes | | PCIe-2.0 (16x) | ~32 GB/s over 16-Lanes ( mode 16x ) | | + PCIe-3.0 25-port 97-lanes non-blocking SwitchFabric ... +over copper/fiber | ~~~ The latest PCIe specification, Gen 3, runs at 8Gbps per serial lane, enabling a 48-lane switch to handle a whopping 96 GBytes/sec. of full duplex peer to peer traffic. [I:] | | ~810 [ns] + InRam-"Network" / many-to-many parallel CPU/Memory "message" passing with less than 810 ns latency any-to-any | |