Approximate cost to access various caches and main

Question

Can anyone give me the approximate time (in nanoseconds) to access L1, L2 and L3 caches, as well as main memory on Intel i7 processors?

While this isn't specifically a programming question, knowing these kinds of speed details is neccessary for some low-latency programming challenges.

Answer 1

Answer 2

Answer 3

~~~~~~| | | smREGs___BW ANALYZE REAL USE-PATTERNs IN PTX-creation PHASE << -Xptxas -v || nvcc -maxrregcount ( w|w/o spillover(s) ) | with about 8.0 TB/s BW [C:Pg.46] | 1.3 TB/s BW shaMEM___ 4B * 32banks * 15 SMs * half 1.4GHz = 1.3 TB/s only on FERMI | 0.1 TB/s BW gloMEM___ | ________________________________________________________________________________________________________________________________________________________________________________________________________________________ +========| DEVICE:3 PERSISTENT gloMEM___ | _|______________________________________________________________________________________________________________________________________________________________________________________________________________________ +======| DEVICE:2 PERSISTENT gloMEM___ | _|______________________________________________________________________________________________________________________________________________________________________________________________________________________ +====| DEVICE:1 PERSISTENT gloMEM___ | _|______________________________________________________________________________________________________________________________________________________________________________________________________________________ +==| DEVICE:0 PERSISTENT gloMEM_____________________________________________________________________+440 [GPU_CLKs]_________________________________________________________________________|_GB| ! | |\ + | o | texMEM___|_\___________________________________texMEM______________________+_______________________________________________________________________________________|_MB| | |\ \ |\ + |\ | | texL2cache_| \ \ .| \_ _ _ _ _ _ _ _texL2cache +370 [GPU_CLKs] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ | \ 256_KB| | | \ \ | \ + |\ ^ \ | | | \ \ | \ + | \ ^ \ | | | \ \ | \ + | \ ^ \ | | texL1cache_| \ \ .| \_ _ _ _ _ _texL1cache +260 [GPU_CLKs] _ _ _ _ _ _ _ _ _ | \_ _ _ _ _^ \ 5_KB| | | \ \ | \ + ^\ ^ \ ^\ \ | | shaMEM + conL3cache_| \ \ | \ _ _ _ _ conL3cache +220 [GPU_CLKs] ^ \ ^ \ ^ \ \ 32_KB| | | \ \ | \ ^\ + ^ \ ^ \ ^ \ \ | | | \ \ | \ ^ \ + ^ \ ^ \ ^ \ \ | | ______________________|__________\_\_______________________|__________\_____^__\________+__________________________________________\_________\_____\________________________________| | +220 [GPU-CLKs]_| |_ _ _ ___|\ \ \_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \ _ _ _ _\_ _ _ _+220 [GPU_CLKs] on re-use at some +50 GPU_CLKs _IF_ a FETCH from yet-in-shaL2cache | L2-on-re-use-only +80 [GPU-CLKs]_| 64 KB L2_|_ _ _ __|\\ \ \_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \ _ _ _ _\_ _ _ + 80 [GPU_CLKs] on re-use from L1-cached (HIT) _IF_ a FETCH from yet-in-shaL1cache | L1-on-re-use-only +40 [GPU-CLKs]_| 8 KB L1_|_ _ _ _|\\\ \_\__________________________________\________\_____+ 40 [GPU_CLKs]_____________________________________________________________________________| | L1-on-re-use-only + 8 [GPU-CLKs]_| 2 KB L1_|__________|\\\\__________\_\__________________________________\________\____+ 8 [GPU_CLKs]_________________________________________________________conL1cache 2_KB| | on-chip|smREG +22 [GPU-CLKs]_| |t[0_______^:~~~~~~~~~~~~~~~~\:________] |CC- MAX |_|_|_|_|_|_|_|_|_|_|_| |t[1_______^ :________] |2.x 63 |_|_|_|_|_|_|_|_|_|_|_| |t[2_______^ :________] |1.x 128 |_|_|_|_|_|_|_|_|_|_|_| |t[3_______^ :________] |3.5 255 REGISTERs|_|_|_|_|_|_|_|_| |t[4_______^ :________] | per|_|_|_|_|_|_|_|_|_|_|_| |t[5_______^ :________] | Thread_|_|_|_|_|_|_|_|_|_| |t[6_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| |t[7_______^ 1stHalf-WARP :________]______________ | |_|_|_|_|_|_|_|_|_|_|_| |t[ 8_______^:~~~~~~~~~~~~~~~~~:________] | |_|_|_|_|_|_|_|_|_|_|_| |t[ 9_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| |t[ A_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| |t[ B_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| |t[ C_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| |t[ D_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| |t[ E_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| W0..|t[ F_______^____________WARP__:________]_____________ | |_|_|_|_|_|_|_|_|_|_|_| .............. | |_|_|_|_|_|_|_|_|_|_|_| ............|t[0_______^:~~~~~~~~~~~~~~~\:________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[1_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[2_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[3_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[4_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[5_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[6_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[7_______^ 1stHalf-WARP :________]______________ | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ 8_______^:~~~~~~~~~~~~~~~~:________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ 9_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ A_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ B_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ C_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ D_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ............|t[ E_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| W1..............|t[ F_______^___________WARP__:________]_____________ | |_|_|_|_|_|_|_|_|_|_|_| .................................................... | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[0_______^:~~~~~~~~~~~~~~~\:________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[1_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[2_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[3_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[4_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[5_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[6_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[7_______^ 1stHalf-WARP :________]______________ | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ 8_______^:~~~~~~~~~~~~~~~~:________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ 9_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ A_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ B_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ C_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ D_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_| ...................................................|t[ E_______^ :________] | |_|_|_|_|_|_|_|_|_|_|_|tBlock Wn....................................................|t[ F_______^___________WARP__:________]_____________ | | ________________ °°°°°°°°°°°°°°°°°°°°°°°°°°~~~~~~~~~~°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°°° | / \ CC-2.0

Answer 4

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Answer 6