Approximate cost to access various caches and main

Question

Can anyone give me the approximate time (in nanoseconds) to access L1, L2 and L3 caches, as well as main memory on Intel i7 processors?

While this isn't specifically a programming question, knowing these kinds of speed details is neccessary for some low-latency programming challenges.

Answer 1

Cost to access various memories in a pretty page

• See this page presenting the memory latency decrease from 1990 to 2020.

Summary

1. Values having decreased but are stabilized since 2005

           1 ns        L1 cache
           3 ns        Branch mispredict
           4 ns        L2 cache
          17 ns        Mutex lock/unlock
         100 ns        Main memory (RAM)
       2 000 ns (2µs)  1KB Zippy-compress
   

2. Still some improvements, prediction for 2020

      16 000 ns (16µs) SSD random read (olibre's note: should be less)
     500 000 ns (½ms)  Round trip in datacenter
   2 000 000 ns (2ms)  HDD random read (seek)
   

See also other sources

• What every programmer should know about memory from Ulrich Drepper (2007)
  Old but still an excellent deep explanation about memory hardware and software interaction.
  • Full PDF (114 pages)
    • Comments on LWN about PDF version
    • Another ones
  • Seven posts on LWN + Comments
    • Part 1 - Introduction
    • Part 2 - Cache
    • Part 3 - Virtual Memory
    • Part 4 - NUMA support
    • Part 5 - What programmers can do
    • Part 6 - More things programmers can do
    • Part 7 - Memory performance tools
• Post The Infinite Space Between Words in codinghorror.com based on book Systems Performance: Enterprise and the Cloud
• Click to each processor listed on http://www.7-cpu.com/ to see the L1/L2/L3/RAM/... latencies (e.g. Haswell i7-4770 has L1=1ns, L2=3ns, L3=10ns, RAM=67ns, BranchMisprediction=4ns)
• http://idarkside.org/posts/numbers-you-should-know/

See also

For further understanding, I recommend the excellent presentation of modern cache architectures (June 2014) from Gerhard Wellein, Hannes Hofmann and Dietmar Fey at University Erlangen-Nürnberg.

French speaking people may appreciate an article by SpaceFox comparing a processor with a developer both waiting for information required to continue to work.

Answer 2

Answer 3

Answer 4

Answer 5

Answer 6

Look at this "staircase" plot, perfectly illustrating different access times (in terms of clock tics). Notice the red CPU having an additional "step", probably because it has L4 (while others don't).

Taken from this Extremetech article.

In computer science this is called "I/O complexity".