We have a long and complicated Makefile in our build system. Is there a good way to trace exactly which targets get executed for a given make invocation?
相关问题
- CMakeList file to generate LLVM bitcode file from
- Makefile to compile lists of source files
- Have make fail if unit tests fail
- C++ - Compiling multiple files
- Trigger missing dependencies in (parallel) GNU mak
相关文章
- How to arrange a Makefile to compile a kernel modu
- Makefile and use of $$
- Makefile: all vs default targets
- Automake Variables to tidy up Makefile.am
- How do I check the exit status of a Makefile shell
- Marking a makefile dependency as optional or other
- How to instruct Makefile to use different compiler
- Why does this makefile execute a target on 'ma
Use
make -d
ormake --debug[=flags]
options:Another option is to use remake - a patched version of GNU Make that adds improved error reporting, the ability to trace execution, and a debugger.
You can get some information about what targets are being built and why by redefining the SHELL variable in GNU make:
For example, in
trace-targets.mk
:Running
trace-targets.mk
after clean:Then running
trace-targets.mk
again without cleaning:Credit by John Graham-Cumming who described this method in Tracing rule execution in GNU Make.
ElectricMake can generate an XML-marked-up version of your build log with lots of information that would help in this situation:
@
modifier).Here's a sample of that output:
How to Quickly Navigate an Unfamiliar Makefile shows an example of using the annotated build log to find your way around a makefile.
Data Mining ElectricAccelerator Annotation shows how you can use the annotated build log to generate a bill-of-materials for the build.
ElectricMake is GNU Make compatible, so it can process makefiles that work with GNU make.
Disclaimer: I'm the architect and lead developer of ElectricAccelerator.