VHDL extend string literal to std_logic_vector

Question

I am trying to convert a string literal like B"101" to C_NO_OF_CHANNELS bits std_logic_vector.

Doing:

library ieee, std, switch_core;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

std_logic_vector(resize(unsigned(B"101"), C_NO_OF_CHANNELS))

raises:

Type conversion (to UNSIGNED) can not have string literal operand.

Answer 1

Between Paebbels comment and wahab's answer there are almost two working ways of converting the bit string literal to a resized std_logic_vector. Both methods can be corrected.

Paebbels' (corrected) method requires converting the bit string to an integer value first then using to_unsigned to convert the (natural) value to unsigned, then type converting to std_logic_vector:

std_logic_vector(to_unsigned (to_integer(unsigned'(B"101")), C_NO_OF_CHANNELS)); -- works

wahab's corrected and simplified method (using a qualified expression):

std_logic_vector(resize(unsigned'(B"101"), C_NO_OF_CHANNELS)); -- works

A Minimal, Complete, and Verifiable example that can be used to demonstrate both:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity extend is
end entity;

architecture foo of extend is
constant  C_NO_OF_CHANNELS:     natural := 42;
signal target: std_logic_vector (C_NO_OF_CHANNELS - 1 downto 0) := 
        -- std_logic_vector(resize(unsigned(std_logic_vector'(B"101")), C_NO_OF_CHANNELS)); -- original - doesn't work
        -- std_logic_vector(to_unsigned (to_integer(unsigned'(B"101")), C_NO_OF_CHANNELS)); -- works
        std_logic_vector(resize(unsigned'(B"101"), C_NO_OF_CHANNELS)); -- works
begin
end architecture;

Note a constant value for C_NO_OF_CHANNELS has been provided.

The corrected wahab expression uses a qualified expression to disambiguate between two possible resize functions (signed and unsigned) the result of either capable of being type converted to std_logic_vector.

Answer 2

Try this:

std_logic_vector(resize(unsigned(std_logic_vector'(B"101")), C_NO_OF_CHANNELS))