How to write a makefile to generate object files a

Question

Now to proceed further I need to change the presentation of existing Makefile.

Presently I am using:

~/Linuz/src: 1.c, 2.c, 3.c ...

~/Linuz/inc: abc.h, xyz.h

and makefile is in: ~/Linuz/some_other_dir/

But need to change the structure.

1. Want to create a library from (~/Linuz/src/ and ~/linuz/inc)
2. Library will be used to get executable. Application source files(.c files) are in ~/Linuz/app/
3. ~/Linuz/bin/ should be created during compilation to store all the object files and executable file.

Any suggestions ??

My makefile looks like this:

all: Library.a

%.o: ../src/%.c

    $(CC) $(CFLAGS) -I../inc/ -c -o $@ $^

Library.a:  $(SRC_DIR)/1.c $(SRC_DIR)/2.c $(SRC_DIR)/3.c $(SRC_DIR)/4.c $(SRC_DIR)/5.c

    $(CC) $(LDFLAGS) -o $@ $^

all: prog

%.o: ./*.c

    $(CC) $(CFLAGS) -ILibrary.a -c -o $@ $^


prog:   $(APP_DIR)/app1.c $(APP_DIR)/app2.c $(APP_DIR)/app3.c

clean:
    rm -f *.o my_program

Answer 1

Let assume that your code architecture looks like that:

└── linuz
    ├── app
    │   ├── app1.c
    │   ├── app2.c
    │   └── app3.c
    ├── bin
    ├── inc
    │   └── any.h
    ├── some_other_dir
    │   └── Makefile
    └── src
        ├── 1.c
        ├── 2.c
        └── 3.c

So your Makefile could be:

all: ../bin/libmy_lib.a ../bin/my_program


../bin/my_lib_%.o: ../src/%.c
    $(CC) $(CFLAGS) -I../inc -c -o $@ $^

../bin/libmy_lib.a: ../bin/my_lib_1.o ../bin/my_lib_2.o  ../bin/my_lib_3.o
    ar rcs $@ $^

../bin/my_app_%.o: ../app/%.c
    $(CC) $(CFLAGS) -I../inc -c -o $@ $^

../bin/my_program: ../bin/my_app_app1.o ../bin/my_app_app2.o  ../bin/my_app_app3.o ../bin/libmy_lib.a
    $(CC) $(LDFLAGS) -L../bin/ -lmy_lib -o $@ $^


clean:
    rm -f ../bin/*.o ../bin/libmy_lib.a ../bin/my_program

For the explanation, refer to your previous question