VHDL - init std_logic_vector array from HEX file

Question

I have simple "RAM" implemented as:

type memory_array is array(31 downto 0) of std_logic_vector(7 downto 0);
signal ram : memory_array;

I would like to init it's content from HEX file. I wonder about reading the file like:

ram_init: process
    file file_ptr : text;
    variable line_text : string(1 to 14);
    variable line_num : line;
    variable lines_read : integer := 0;
    variable char : character;
    variable tmp_hexnum : string(1 to 2);
begin
    file_open(file_ptr,"../RAM.HEX",READ_MODE);
    while (not endfile(file_ptr)) loop
        readline (file_ptr,line_num);
        READ (line_num,line_text);
        if (lines_read < 32) then
            tmp_hexnum := line_text(10 to 11);
            -- ram(lines_read) <= tmp_hexnum;
            lines_read := lines_read + 1;
            wait for 10 ns;
        end if;
    end loop;
    file_close(file_ptr);
    wait;
end process;

The problem is (if this code above would works, which I don't even know), how to convert the tmp_hexnum string to std_logic_vector.

Please have patience with me, VHDL beginner.

Answer 1

Converting a string of variable length to std_logic_vector with length as 4 * length of string, can be done with the function below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
-- Convert string to std_logic_vector, assuming characters in '0' to '9',
-- 'A' to 'F', or 'a' to 'f'.
function str_to_slv(str : string) return std_logic_vector is
  alias str_norm : string(1 to str'length) is str;
  variable char_v : character;
  variable val_of_char_v : natural;
  variable res_v : std_logic_vector(4 * str'length - 1 downto 0);
begin
  for str_norm_idx in str_norm'range loop
    char_v := str_norm(str_norm_idx);
    case char_v is
      when '0' to '9' => val_of_char_v := character'pos(char_v) - character'pos('0');
      when 'A' to 'F' => val_of_char_v := character'pos(char_v) - character'pos('A') + 10;
      when 'a' to 'f' => val_of_char_v := character'pos(char_v) - character'pos('a') + 10;
      when others => report "str_to_slv: Invalid characters for convert" severity ERROR;
    end case;
    res_v(res_v'left - 4 * str_norm_idx + 4 downto res_v'left - 4 * str_norm_idx + 1) :=
      std_logic_vector(to_unsigned(val_of_char_v, 4));
  end loop;
  return res_v;
end function;

Answer 2

The first mistake is to use a process : if you attempt to synthesise the design, the process won't do anything until the design is built and running; which is far too late to read a file!

Instead, wrap the init code in a function, and use that to initialise the memory

signal ram : memory_array := my_ram_init(filename => "../RAM.HEX");

This will work in simulation, and many synthesis tools will infer a RAM and initialise it correctly. If you declared a constant instead of a signal, this would create a ROM instead of a RAM.

Anyway the function looks a bit like

function my_ram_init(filename : string) return memory_array is
   variable temp : memory_array;
   -- other variables
begin
   file_open(...);
   -- you have a good handle on the function body
   file_close(...);
   return temp;
end function;

leaving you with the original problem :

temp(lines_read) <= to_slv(tmp_hexnum);

writing the to_slv function. There ought to be a standard library of these, but for some reason there isn't a universally accepted one. So, here's a start...

function to_slv (tmp_hexnum : string) return std_logic_vector is
   variable temp  : std_logic_vector(7 downto 0);
   variable digit : natural;
begin
   for i in tmp_hexnum'range loop
      case tmp_hexnum(i) is
      when '0' .. '9' => 
         digit := Character'pos(tmp_hexnum(i)) - Character'pos('0');
      when 'A' .. 'F' => 
         digit := Character'pos(tmp_hexnum(i)) - Character'pos('A');
      when others => digit <= 0;
      end case;
      temp(i*4+3 downto i*4) := std_logic_vector(to_unsigned(digit));
   end loop;
   return temp;
end function;

Answer 3

Your (both) answers helped me a lot. But it seems not working.

function ram_init(filename : string) return memory_array is
    variable temp : memory_array;
    file file_ptr : text;
    variable line_line : line;
    variable line_text : string(1 to 14);
    variable tmp_hexnum : string(1 to 2);
    variable lines_read : integer := 0;
    begin
        file_open(file_ptr,filename,READ_MODE);
        while (lines_read < 32 and not endfile(file_ptr)) loop
            readline (file_ptr,line_line);
            read (line_line,line_text);
            tmp_hexnum := line_text(10 to 11);
            temp(lines_read) := hex_to_bin(tmp_hexnum);
            lines_read := lines_read + 1;
        end loop;
        file_close(file_ptr);
    return temp;
end function;
signal ram : memory_array := ram_init(filename=>"../RAM.HEX");

If I set tmp_hexnum to e.g. "0A", it's OK, but reading from file do not fill the RAM.

Can you please check the file part for me, too?