Error VHDL Quartus: can't determine definition

Question

I write this vhdl code but I have this problems:

Error (10327): VHDL error at CircuitoCombinatorio.vhd(16): can't determine definition of operator ""="" -- found 0 possible definitions.

Line error is: if(areset="1") then.

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity CircuitoComparatore is
    port(a:in std_logic_vector(2 downto 0);
         clk,areset:in std_logic;
          u: out std_logic );
end CircuitoComparatore;

architecture ACircuitoComparatore of CircuitoComparatore is
    signal c,d: std_logic_vector(2 downto 0);
    begin
    c<=a+"011";
    reg:process(areset,clk)
        begin
        if(areset="1") then
            d<="000";
        elsif(ck'event and ck="1") then
            d<=c;
        end if;
    end process reg;
   CMP:process(a,d)
   begin
   if(a>d) then
        u<="001";
    else 
        u<="000";
    end if;
    end process CMP;
end ACircuitoComparatore;   

Answer 1

Analyzing your design specification unchanged:

ghdl -a --ieee=synopsys -fexplicit acircuit.vhdl acircuit.vhdl:16:18: no function declarations for operator "=" acircuit.vhdl:18:15: no declaration for "ck" acircuit.vhdl:25:12: can't match string literal "001" with type enumeration subtype "std_logic" acircuit.vhdl:27:12: can't match string literal "000" with type enumeration subtype "std_logic" ghdl: compilation error

When corrected:

 1  Library ieee;
 2  use ieee.std_logic_1164.all;
 3  use ieee.std_logic_unsigned.all;
 4  Entity CircuitoComparatore is
 5      port(a:in std_logic_vector(2 downto 0);
 6           clk,areset:in std_logic;
 7            u: out std_logic );
 8  end CircuitoComparatore;
 9  
10  architecture ACircuitoComparatore of CircuitoComparatore is
11      signal c,d: std_logic_vector(2 downto 0);
12      begin
13      c<=a+"011";
14      reg:process(areset,clk)
15          begin
16          if(areset='1') then       -- was (areset="1")
17              d<="000";
18          elsif(clk'event and clk='1') then -- was (ck'event and ck="1")
19              d<=c;
20          end if;
21      end process reg;
22     CMP:process(a,d)
23     begin
24     if(a>d) then
25          u<='1';                   -- was u<="001";
26      else 
27          u<='0';                   -- was u<="001";
28      end if;
29      end process CMP;
30  end ACircuitoComparatore;   

your design specification analyzes.

The first error on Line 16 occurs because there is no declared equality operator that compares between std_logic and string. areset is declared as std_logic, which uses enumeration values that are character literals. String values are associated with string based types such as std_logic_vector, for example Line 17 `d<="000".

Line 18 makes the same mistake equality testing ck="1" while ck should also be the declared clock clk.

Line 25 and 27 both assign a string value to std_logic type when the should assign an enumeration value (a character type).

You could also note that the condition in an if statement is a boolean_expression (returns a boolean value), and expressions only require enclosing in matching left and right parenthesis to control association and evaluation order. VHDL has fixed precedence with multiple operators of the same precedence. Neither condition in your two if statements require parenthesis. 'permission' to use parenthesis where they are not needed is a side effect of requiring them where they are needed in the EBNF syntax found in the LRM section on expressions. Adding them where not required has the effect of creating an expression inside and expression where there is no other distinction made in outer expression. At best case it slows down analysis, and at worst slows down simulation (if not optimized out by elaboration, an implementation dependent issue). In other words the bigger and more complex the expression the more penalty you pay in terms of analysis or simulation time and the effects are cumulative across your design model.

Answer 2

areset is std_logic so compare must be with '1', not "1"; same goes below, where you may want to change ck to clk.

Fix is also required for u below, which is std_logic but assigned with several bits using "001".

Answer 3

First of all, in the line elsif(ck'event and ck="1") then you should use 'clk' rather than 'ck' and the parentheses should be like '1' not "1" in the lines if(areset="1") then and elsif(ck'event and ck="1") then.

Answer 4

since the signal areset is a single bit signal, you have to use '1' instead of "1".Double quotes is used for buses(more than 1 bit). Also replace the 'ck' with 'clk'(which is a typo). Also, you can use the statement (rising_edge(clk)) instead of (clk'event and clk="1") in your code.