VHDL-“Signal cannot be synthesized, bad synchronou

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• ACTIV HDL - VHDL-“Signal cannot be synthesized, bad synchronous description” 1 answer

I have a error while Synthesize this code in Xillinx. This error is: "Signal Z_1 cannot be synthesized, bad synchronous description"

entity uk3 is
     port(
         rst : in BIT;
         C : in INTEGER;
         clk : in BIT;
         S : out INTEGER
         );
end uk3;

--}} End of automatically maintained section

architecture uk3 of uk3 is
begin
    process (C,clk,rst)
    variable Z_1 : integer:=0;
    begin
        if rst='1' then Z_1:=0;
        elsif rst='0'and clk'event and clk='1'and C=1
            then 
            Z_1:=Z_1 + 1;
        elsif rst='0'and clk'event and clk='1'and C=2
            then
            Z_1:=Z_1 + 2;   
        else
            Z_1:=Z_1;
        end if;
        S<=Z_1;
        end process;

     -- enter your statements here --

end uk3;

why? Pls

Answer 1

You probably should properly describe your synchronous process. This is not c/c++, you should use proper template for that, or it will not synthesize. I particular, you should only have one statement sensitive for edge of the clock.

For example:

process (clk,rst)
variable Z_1 : integer:=0;
begin
    if rst='1' then 
        Z_1:=0;
    elsif rising_edge(clk) then
        case C is
            when 1 =>
                Z_1:=Z_1 + 1;
            when 2 => 
                Z_1:=Z_1 + 2;
            when others =>
                null;
        end case;
        S<=Z_1;
    end if;

end process;

Note, that there is no C in sensitivity list, as it is not needed. If there is no rising edge, it will not fire anyway (it is synchronous to rising edge of the clock)

I havn't tested this code, but it should work.

And actually, why don't you make Z_1 signal, instead of variable?