Unnecessary spaces in Verilog Display

问题:

I'm trying to display some 32 bit values in decimal, and this is working fine other than the strange amount of unecessary spaces between my %b and the previous character.

for example: if i have a 32-bit reg a with a decimal value of 33, i'll use something like this

initial
begin
    $display("a=%d;", a);
end

the output in cmd would look similar to this: a= ___________________33;

The line just represents the long blank space between %b and the previous char. Can somebody explain to me why this happens? And how can I get rid of them?

回答1:

In IEEE Std 1800-2012 (21.2.1.3) you can find following information:

When displaying decimal values, leading zeros are suppressed and replaced by spaces. In other radices, leading zeros are always displayed.

That's why you got so many spaces before 33. The simplest way to achieve whay you want would be:

$display("a=%0d;", a);

By adding 0 between % character and d (letter that indicates the radix) the automatic sizing of displayed data is overridden. The result will be printed with minimum possible size.